IC PROCESSOR AM/FM DGTL 100-TQFP

TDA7500A

Manufacturer Part NumberTDA7500A
DescriptionIC PROCESSOR AM/FM DGTL 100-TQFP
ManufacturerSTMicroelectronics
TypeAudio Processor
TDA7500A datasheet
 


Specifications of TDA7500A

ApplicationsAudio SystemsMounting TypeSurface Mount
Package / Case100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
SOFTWARE AM/FM, AUDIO AND SOUND-
PROCESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC (4ADCs, 6DACs)
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE
(SAI)
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE (EMI)
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
12x2 MULTIFUNCTION GENERAL PURPOSE
I/O PORTS
BLOCK DIAGRAM
analog in
ADC-ref
Decimation
Filter
ADCVDD
ADCGND
AVDD
AGND
CLK in
Crystal
Oscillator
6 Ch. Audio Bus
2
receive bit&word clk
SAI 6ch.
Receiver
digital audio in
SPDIF 2ch.
SPDIF audio in
Interface
DSP1 Orpheus Core
including 12 GPIO´s
Dolby B
FM processing,
AM processing,
Traffic memorization
4
Debug Interface
December 2001
DIGITAL AM/FM SIGNAL PROCESSOR
DESCRIPTION
The TDA7500A is an integrated circuit implementing
a fully digital, integrated and advanced solution to
perform the signal processing in front of the power
amplifier and behind the AM/FM tuner or any other
audio source. The chip integrates two 45 MIPs DSP
cores: one for stereo decoding, noise blanking, weak
signal processing and multipath detection and one for
sound processing, Dolby B, echo and noise cancel-
ling for the telephone.
SC
Filter
PLL Clock
Noise
Generator
Decimation
Shaper
Filter
Oversampl.
Filter
RDS
Filter
2ch Sample
Rate
Converter
External Memory Interface
Xchg
X Ram 1024
X Ram 1024
Interf.
Y Ram 1024
Y Ram 1024
P Ram 2048
P Ram 5632
P Rom 256
P Rom 512
TDA7500A
TQFP100 (with slug down)
ORDERING NUMBER: TDA7500A
analog audio out
SC
SC
SC
SC
SC
Filter
Filter
Filter
Filter
Filter
DAC-ref
Noise
Noise
Shaper
Shaper
Oversampl.
Oversampl.
Filter
Filter
RDS
RDS bit/blk Int.
Grp & blk
4
SPI
RDS SPI
sync., error
Demod.
Error corr. RDS blocks
correction
or RDS clk, dat, qual
4
P control
10 word SPI 1
IIC / SPI 1
4
receive stack
Display P
SPI 2
3
6 Channel
2
SAI Transmitter
Audio Bus
8+3
SRAM 4Mx8
17
DRAM 128kx4
Int
DSP0 Orpheus Core
Reset
including 12 GPIO´s
4
VDD
Audio processing,
4
GND
Sound processing,
2
Noise & Echo Canc.
Test
4
Debug Interface
1/40

TDA7500A Summary of contents

  • Page 1

    ... Debug Interface December 2001 DIGITAL AM/FM SIGNAL PROCESSOR DESCRIPTION The TDA7500A is an integrated circuit implementing a fully digital, integrated and advanced solution to perform the signal processing in front of the power amplifier and behind the AM/FM tuner or any other audio source. The chip integrates two 45 MIPs DSP ...

  • Page 2

    ... Separated Debug and Test Interfaces are connected to both DSP cores. The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also available ...

  • Page 3

    ... SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. I SPI Slave Select (Input)/General Purpose I/O (Input/Output). Behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. TDA7500A 2 C bus. If SPI 3/40 ...

  • Page 4

    ... TDA7500A PIN DESCRIPTION (continued) N° Name 14 CLKIN 15 AVDD 16 XTI 17 XTO 18 AGND 19 RDSINT/DSP1_GPIO4 20 RDSARI_SCK/DSP1_GPIO3 21 RDSQAL_SO/DSP1_GPIO2 22 RDSDAT_SI/DSP1_GPIO1 23 RDSCLK_SS/DSP1_GPIO0 24 INT 25 CGND1 26 CVDD1 27 SCRCCD 28 SCRMD 29 DSRA<7> 30 DSRA<6> 4/40 Type Description I Clock Input pin (Input). Clock from external digital audio source to synchronize the internal PLL. Supply pin dedicated to the PLL. ...

  • Page 5

    ... Line<7> (Output). This pin acts as the EMI address line 7 in both SRAM Mode and DRAM Mode O DSP SRAM Address Line<8> (Output)/DSP DRAM Address Line<8> (Output). This pin acts as the EMI address line 8 in both SRAM Mode and DRAM Mode TDA7500A 5/40 ...

  • Page 6

    ... TDA7500A PIN DESCRIPTION (continued) N° Name 46 SRA<9> 47 SRA<10> 48 SRA<11> 49 SRA<12> 50 CGND2 51 CVDD2 52 SRA<13> 53 SRA<14> 54 SRA<15> 55 SRA<16>/DSP0_GPIO8 56 DWR 57 DRD 58 CASALE 59 SDO<2>/SRA<17>/DSP1_GPIO<8> 6/40 Type Description O DSP SRAM Address Line<9> (Output)/DSP DRAM Address Line<9> (Output). This pin acts as the EMI address line 9 in both ...

  • Page 7

    ... I/O. I Debug Port Request Input (Input). Means of entering the Debug mode of operation. I/O Debug Port Serial Output (Input/Output)/ General Purpose I/O (Input/Output). The serial data output for the Debug Port. Optionally it can be used as a general purpose I/O. TDA7500A 7/40 ...

  • Page 8

    ... TDA7500A PIN DESCRIPTION (continued) N° Name 74 DBIN0/OS00/DSP0_GPIO11 75 DBCK0/OS01/DSP0_GPIO9 76 DBRQN0 77 VDD2 78 GND2 79 ADC<0> 80 ADC<1> 81 ADC<2> 82 ADC<3> 83 S2DREF 84 ADCVDDREF 85 ADCREF<2> 86 ADCREF<1> 87 ADCREF<0> 88 ADCVDD 89 ADCGND 90 DAC<0> 91 DAC<1> 92 DAC<2> 93 DAC<3> 94 DAC<4> 95 DAC<5> 8/40 Type Description I/O Debug Port Serial Input/Chip Status 0 (Input/Output)/ General Purpose I/O (Input/Output). The serial data input for the Debug Port is provided when an input ...

  • Page 9

    ... X X input 5VT output 4mA OD X input 5VT output 4mA OD X input 5VT input 5VT output 4mA input 5VT output 4mA PP X input 5VT output 4mA PP TDA7500A Description I/O Comments To be connected to VDD To be connected to GND Ext. Pulldown (1) undefined input 9/40 ...

  • Page 10

    ... TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 11 DSPI: MISOD input DSPI: MISOD output DSP0: GPIO5 input DSP0: GPIO5 output 12 DSPI: MOSID input DSPI: MOSID output DSP0: GPIO6 input DSP0: GPIO6 output 13 DSPI: SSD input DSP0 : GPIO7 input DSP0 : GPIO7 output ...

  • Page 11

    ... PP output 2mA 0/1 output 2mA PP output 2mA 0/1 output 2mA PP output 2mA 0/1 output 2mA PP output 2mA 0/1 output 2mA PP output 2mA 0/1 output 2mA PP output 2mA 0/1 output 2mA PP output 2mA PP supply supply TDA7500A I/O Comments 11/40 ...

  • Page 12

    ... TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 52 EMI SRAM: Add<13> output EMI SRAM: Add<13> output 53 EMI SRAM: Add<14> output EMI SRAM: Add<14> output 54 EMI SRAM: Add<15> output EMI SRAM: Add<15> output 55 EMI SRAM: Add<16> output EMI SRAM: Add<16> output DSP0:GPIO8 input ...

  • Page 13

    ... X analog input analog input analog input Substrate biasing voltage reference voltage reference TDA7500A I/O Comments After boot in debug mode After boot in debug mode After boot in debug mode After boot in debug mode After boot in debug mode After boot in debug mode After boot in ...

  • Page 14

    ... TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 86 ADC: REF<1> input 87 ADC: REF<0> input 88 ADCVDD 89 ADCGND 90 DAC<0> output 91 DAC<1> output 92 DAC<2> output 93 DAC<3> output 94 DAC<4> output 95 DAC<5> output 96 DAC: REF<2> input 97 DAC: REF<1> input 98 DAC: REF<0> input 99 DACGND 100 DACVDD Output PP: Push-Pull/ OD: Open-Drain 5VT input: TTL Five Volt Tolerant Input - Schmitt-trigger for all inputs ...

  • Page 15

    ... Debug DSP1 SPDIF OD: 5V tolerant Open Drain Output EMI Test Condition Test Condition power supply @ 3.3V and T = 125°C j Test Condition power supply @ 3.3V and T = 125°C j TDA7500A DBCK0OS01 DSP0 GPIO9 75 DBIN0OS00 DSP0 GPIO11 74 DBOUT0 DSP0 GPIO10 73 DBRQN1 72 DBCK1_OS11 DSP1 GPIO9 ...

  • Page 16

    ... TDA7500A OSCILLATOR CHARACTERISTICS Symbol Parameter F Max Oscillator Frequency (XTI) OSC GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter l Low Level Input Current without il pullup device l High Level Input Current without ih pullup device I Tri-state Output leakage without oz pull up/down device I 5V Tolerant Tri-state Output ...

  • Page 17

    ... V = 3.3V, measurement bandwidth 10Hz to 53KHz.) amb CC Test Condition AM-Mode -60dB analog input 1KHz; -3dB analog input -3dB analog input TDA7500A Min. Typ. Max. Unit 48 MHz Min. Typ. Max. Unit >50 dB 0.02 ...

  • Page 18

    ... TDA7500A ADC ELECTRICAL CHARACTERISTCS (T 160KHz.) Symbol Parameter Input Voltage Dynamic Range Sampling rate Dynamic Range SNR DAC PERFORMANCE (T = 25°C, V amb 0dB gain, output load 30k ) Symbol Parameter Output voltage dynamic range Sampling rate Attenuation @ 20kHz Dynamic Range SNR Digital Silence ...

  • Page 19

    ... DSP Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 LRCKR (#68) SCKR (#67) SDI0,1,2 (#62, #63, #64) Valid Valid t lrh t sckpl t sdih t lrs t sdis sckr Description DSP LEFT RIGHT MSB-1 (n) LSB(n-1) MSB(word n) TDA7500A t sckph Value Unit 4T DSP 0.35 t sckr 0.35 t sckr MSB-2 ( ...

  • Page 20

    ... TDA7500A Figure 3. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. Figure 5. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. 20/40 ...

  • Page 21

    ... CPHA=1) SCLKD, SCLKM (#6, #10) SCLKD, SCLKM (#6, #10) (CPOL=1, CPHA=0) SCLKD, SCLKM (#6, #10) (CPOL=1, CPHA=1) MISOM, MOSIM (#7, #8) MISOD, MOSID (#11, #12) Description MASTER SLAVE MASTER SLAVE MSB Internal Strobe for Data Capture TDA7500A Min Value Unit 12T ns DSP 0.5t ns sclk 0.5t ns sclk ...

  • Page 22

    ... TDA7500A Debug Port Interface No. 1 DBCK rise time 2 DBCK fall time 3 DBCK Low 4 DBCK High 5 DBCK Cycle Time 6 DBRQN Asserted to DBOUT (ACK) Asserted 7 DBCK High to DBOUT Valid 8 DBCK High to DBOUT Invalid 9 DBIN Valid to DBCK Low (Set-up) 10 DBCK Low to DBIN Invalid (Hold) ...

  • Page 23

    ... Figure 9. Debug Port Data I/O to Status Timing. Figure 10. Debug Port Read Timing. Figure 11. Debug Port DBCK Next Command After Read Register Timing. TDA7500A 23/40 ...

  • Page 24

    ... TDA7500A EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE Characteristics Page Mode Cycle Time RAS or RD Assertion to Data Valid CAS Assertion to Data Valid Column Address Valid to Data Valid CAS Assertion to Data Active RAS Assertion Pulse Width (Note 1) (Page Mode Access Only) RAS Assertion Pulse Width (Single Access Only) ...

  • Page 25

    ... WR Assertion to Data Active Figure 12. External Memory Interface SRAM Read Cycle. SRA_D [7:0] SRA_D [13:8] ALE DRD Figure 13. External Memory Interface SRAM Write Cycle. SRA [7:0] SRA [13:8] ALE DWR add. [7:0] add. [13:8] add. [7:0] add. [13:8] TDA7500A 40MHz Min. Max ...

  • Page 26

    ... TDA7500A Figure 14. DRAM Read Cycle. DRA [8:0] Row address 1 RAS CAS DRD DRD [3:0] Figure 15. DRAM Write Cycle. Row address 1 DRA [8:0] RAS CAS DWR DRD[3:0] 26/40 Column address 2 Column address 1 nibble 1 Column address 1 Column address 2 nibble 1 nibble 2 Row address 2 nibble 2 ...

  • Page 27

    ... Full Scale, 20 bit inp 1 kHz - bit inp.,A-Weighted 1 kHz - bit inp.,A-Weighted @ -3 dB from 0 to 20kHz @24.1kHz Fsout = 44.1 kHz Test Condition First mode Second mode (T DSP is the period of the dsp core) TDA7500A Min. Typ. Max. Unit -98 dB -101 dB -98 dB -98 ...

  • Page 28

    ... TDA7500A TIMING Figure 16. Definition of Timing for the I Symbol Parameter F SCLl clock frequency SCL t Bus free between a STOP and BUF Start Condition t Hold time (repeated) START HD:STA condition. After this period, the first clock pulse is generated t LOW period of the SCL clock LOW ...

  • Page 29

    ... FUNCTIONAL DESCRIPTION The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associ- ated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder. 24-BIT DSP CORE The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of digital data coming via SPDIF or SAI ...

  • Page 30

    ... TDA7500A I2C and SPI interface XCHG Interface for DSP to DSP communication External Memory Interface (DRAM/SRAM) for time-delay and traffic information Double Debug Port DATA AND PROGRAM MEMORY Both DSP0 and DSP1 have Data and Program memories attached to them. Each of the memories are described below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1 ...

  • Page 31

    ... X-Peripherals $FFC0 $FFBF Not Accessible Not Accessible $0800 $07FF $0400 $03FF X-RAM Y-RAM $0100 $00FF Boot-ROM $0000 DSP0 TDA7500A P-Space X-Space Y-Space $FFFF X-Peripherals $FFC0 $FFBF Not Accessible Not Accessible Not Accessible P-RAM $0400 $03FF X-RAM Y-RAM DSP1 31/40 ...

  • Page 32

    ... TDA7500A The features of the EMI are listed below. Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM Data word length bits for DRAM Data word length bits for SRAM DRAM address lines means 2 Refresh rate for DRAM can be chosen among eight divider factor SRAM relative addressing mode ...

  • Page 33

    ... PLL. As the usual internal sample rate of TDA7500A is around 48.51 kHz, the ASRC works with the common input signals only in upsampling mode. There is no need to explicitly program the input and output sample rates, as the ASRC solves this problem with an automatic Digital Ratio Locked Loop ...

  • Page 34

    ... Power Supply SOFTWARE FEATURES A great flexibility is guaranteed by the two programmable DSP cores. A list of the main software functions which can be implemented in the TDA7500A is enclosed hereafter. A block diagram of the audio process- ing flow is shown in Fig. 19 below. Figure 19. Software Block Diagram of Audio & Sound Processing ...

  • Page 35

    ... TDA7501 and fed to the TDA7500A. A block diagram of the system is shown in Fig. 20 below. The TDA7500A converts all the analog signals into digital domain and performs AM/FM processing and audio/sound processing ...

  • Page 36

    ... FRONT END Clock Scheme When TDA7500A is used in AD/FM mode the following scheme is choosen in order to avoid harmonics inside the FM band. Parts of the system are directly clocked by the crystal oscillator, whereas other parts are driven by the pll oscillator. Thanks to this it is possible to process any audio source as well analog as digital in parallel to record FM mono for traffic informations, telephone resp ...

  • Page 37

    ... ADCVDOREF DAC0 OUT0 DAC1 OUT1 ADCREF2 DAC2 OUT2 DAC3 OUT3 ADCREF1 DAC4 OUT4 DAC5 OUT5 ADCREF0 S2DREF DACREF2 DACVCC DACREF1 TDA7500A CGND2 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 DSRA0 DSRA1 DSRA2 DSRA3 DSRA4 DSRA5 ...

  • Page 38

    ... TDA7500A PACKAGE MARKING 38/40 ...

  • Page 39

    ... MAX. 0.063 0.006 0.055 0.057 0.009 0.011 0.008 0.630 0.551 0.472 0.020 0.630 0.551 0.472 0.388 0.024 0.030 0.039 TQFP100 (14x14x1.40mm) with Slug Down (10x10mm) 0.003 TQFP100M S TDA7500A OUTLINE AND MECHANICAL DATA SEATING C PLANE ccc 0.25mm .010 inch GAGE PLANE 39/40 ...

  • Page 40

    ... TDA7500A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...