TDA7500A STMicroelectronics, TDA7500A Datasheet - Page 29

• Manufacturer Part Number: TDA7500A
• Description: IC PROCESSOR AM/FM DGTL 100-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of TDA7500A

• Applications: Audio Systems
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associ-
ated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder.
24-BIT DSP CORE
The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of
digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for an-
alog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement
and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1
is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a
different input source is selected.
Some capabilities of the DSPs are listed below:
DSP PERIPHERALS
There are a number of peripherals that are tightly coupled to the two DSP Cores. Same of the peripherals are
connected to DSP 0 others are connected to DSP1.
Single cycle multiply and accumulate with convergent rounding and condition code generation
2 x 56-bit Accumulators
Double precision multiply
Scaling and saturation arithmetic
48-bit or 2 x 24-bit parallel moves
64 interrupt vector locations
Fast or long interrupts possible
Programmable interrupt priorities and masking
8 each of Address Registers, Address Offset Registers and Address Modulo Registers
Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic
Post-increment or decrement by 1 or by offset, Index by offset, predecrement address
Repeat instruction and zero overhead DO loops
Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines
Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test
4 pin serial debug interface
Debug ccess to all internal registers, buses and memory locations
5 word deep program address history FIFO
Hardware and software breakpoints for both program and data memory accesses
Debug Single stepping, Instruction injection and Disassembly of program memory
5.5k x 24-Bit Program RAM for DSP0
1k x 24-Bit X-Data RAM for DSP0
1k x 24-Bit Y-Data RAM for DSP0
2k x 24-Bit Program RAM for DSP1
1k x 24-Bit X-Data RAM for DSP1
1k x 24-Bit Y-Data RAM for DSP1
Serial Audio Interface (SAI)
SPDIF receiver with sampling rate conversion
TDA7500A
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