TDA7500A STMicroelectronics, TDA7500A Datasheet - Page 7

• Manufacturer Part Number: TDA7500A
• Description: IC PROCESSOR AM/FM DGTL 100-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of TDA7500A

• Applications: Audio Systems
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN DESCRIPTION (continued)
N°
60
61
62
63
64
65
66
67
68
69
70
71
72
73
SDO<2>/SRA<18>/DSP1_GPIO<7>
SDO<0>/SRA<19>
SDI<2>/SRA<20>/DSP1_GPIO<6>
SDI<1>/SRA<21>/RAS/DSP1_GPIO<5>
SDI<0>/SRCCDC
SCKT
LRCKT
SCKR
LRCKR
DBOUT1/DSP1_GPIO10
DBIN1/OS10/DSP1_GPIO11
DBCK1/OS11/DSP1_GPIO9
DBRQN1
DBOUT0/DSP0_GPIO10
Name
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
SAI Outputs (Output)/EMI SRAM Address Line<18> (Output)/
General Purpose I/O (Input/Output). One stereo channel SAI
data output in SAI mode. EMI address line 18 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
One stereo channel SAI data output in SAI mode. EMI address
line 19 in SRAM Mode.
SAI Input (Input)/EMI SRAM Address Line<20> (Output)/
General Purpose I/O (Input/Output). One stereo channel SAI
data input in SAI mode. EMI address line 20 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
SAI Input (Input)/EMI SRAM Address Line<21> (Output)/DRAM
Row Address Strobe (Output)/General Purpose I/O (Input/
Output). One stereo channel SAI data input in SAI mode. EMI
address line 21 in SRAM Mode. When in DRAM Mode this pin
acts as the row address strobe. Optionally it can be used as a
general purpose I/O.
SAI Input (Input)/SPDIF Input 3 (Input). One stereo channel SAI
data input in SAI mode. Stereo SPDIF input intended to connect
a digital audio source like a CD changer in SPDIF mode.
SAI transmitter Bit Clock (Input/Output). SAI transmitter bit clock.
Master or slave.
SAI transmitter Left-Right Clock (Input/Output). SAI transmitter
Left-Right clock. Can be master or slave mode.
SAI receiver Bit Clock (Input). SAI receiver bit clock. Slave only.
SAI receiver Left-Right Clock (Input/Output). SAI receiver Left-
Right clock. Slave only.
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
Purpose I/O (Input/Output). The serial data input for the Debug
Port is provided when an input. When an output, together with
OS1 provides information about the chip status. Optionally it can
be used as a general purpose I/O.
Purpose I/O (Input/Output). The serial clock for the Debug Port
is provided when an input. When an output, together with OS0
provides information about the chip status. Optionally it can be
used as a general purpose I/O.
Debug Port Request Input (Input). Means of entering the Debug
mode of operation.
(Input/Output). The serial data output for the Debug Port.
Optionally it can be used as a general purpose I/O.
SAI Output (Output)/EMI SRAM Address Line<19> (Output).
Debug Port Serial Output (Input/Output)/ General Purpose I/O
Debug Port Serial Input/Chip Status 0 (Input/Output)/ General
Debug Port Bit Clock/Chip Status 1 (Input/Output)/General
Debug Port Serial Output (Input/Output)/ General Purpose I/O
Description
TDA7500A
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