DIT4192IPWG4

... PACKAGE: TSSOP-28 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. ...

ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage, V .............................................................. +6. ............................................................... +6.5V IO Input Current ................................................................................... 10mA Digital Input Voltage .......................................................... –0.2V to +5.5V Digital Output Voltage ............................................ –0. Power Dissipation .......................................................................... 300mW Operating Temperature Range ...................................... –40 ...

ELECTRICAL CHARACTERISTICS All specifications + +5V, and PARAMETER DIGITAL CHARACTERISTICS Applies to All Digital I/O Except TX+ and TX– High-Level Input Voltage Low-Level Input Voltage High-Level Output ...

PIN CONFIGURATION: Software Mode (MODE = 0) Top View NC 1 CDOUT 2 CCLK 3 CDIN MCLK 6 V DIT4192 7 IO DGND 8 RXP SCLK 11 SYNC 12 SDATA PIN ...

GENERAL DESCRIPTION The DIT4192 is a complete digital audio transmitter, suitable for both professional and consumer audio applications. Sam- pling rates up to 192kHz are supported. The DIT4192 com- plies with the requirements for the AES-3, IEC-60958, and EIAJ CP1201 ...

Frame 191 X Channel A Channel B Bits Preamble Aux Data FIGURE 3. AES-3 Frame Format. MASTER CLOCK The DIT4192 requires a master clock for operation. This clock must be supplied at the MCLK input (pin 6). ...

The SYNC pin is also used as a data latch clock for the channel status, user, and validity data inputs in Hardware mode, and the user data input in Software mode. SLAVE OR MASTER MODE ...

For Software mode, Control Register 03 audio data format selection. Data word length may be set to 16, 18, 20 bits using the WLEN0 and WLEN1 bits. Several format parameters, including SCLK sampling edge, data delay from the ...

INPUT FUNCTION COPY Copy Status L Generation Status COPY AUDIO Audio Data Status AUDIO Status 0 Digital (or Linear PCM) Audio Data 1 Non-Audio or Encoded Audio Data EMPH Pre-Emphasis Status EMPH Status 0 Pre-emphasis bits ...

LINE DRIVER OUTPUTS The DIT4192 includes a balanced line driver. The line driver outputs are TX– (pin 17) and TX+ (pin 18). In Software mode, the line driver input is taken from either the output of the on- chip AES-3 ...

READ OPERATION Figure 7 shows an illustration of the read operation for the control port. You may read one register or buffer address at a time, or use the auto-increment capability built into the control port to perform block reads. ...

CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY) This section defines the control registers used to configure the DIT4192, as well as the status register used to indicate an interrupt source. Register 00 : Reserved for Factory Use H Bit 7 (MSB) ...

SCLKR Master Mode SCLK Frequency (Defaults to 0) When set to 0, the SCLK frequency is set to 64 • When set to 1, the SCLK frequency is set to 128 • WLEN[1:0] Audio ...

BTD Buffer Transfer Disable (Defaults to 0) When set to 0, User Access (UA) to Transmit- ter Access (TA) Buffer transfers are enabled. When set to 1, User Access (UA) to Transmit- ter Access (TA) Buffer transfers are disabled. Register ...

ADDRESS CS BIT 0 (HEX) Byte MSB 08 A0 PRO 09 B0 PRO MODE CH MODE MODE CH MODE 0C A2 AUX 0D B2 AUX 0E A3 reserved 0F B3 reserved 10 A4 REF ...

ADDRESS CS BIT 0 (HEX) Byte MSB 8 A0 PRO = PRO = CAT CODE CAT CODE 0B B1 CAT CODE CAT CODE 0C A2 SOURCE SOURCE 0D B2 SOURCE SOURCE ...

CHANNEL STATUS BUFFER TRANSFER INTERRUPT This interrupt occurs when a channel status buffer transfer has been completed. The buffer transfer process was de- scribed in detail in the previous section of this data sheet. This interrupt may be used by ...

Digital Audio Source (A/D Converter, DSP) Hardwired Control or Dedicated Logic or Host Controlled Audio Master Clock Generator FIGURE 11. Typical Circuit Configuration, Hardware Mode. The line driver outputs may be connected to cable or fiber optic transmission media in ...

Dual-Wire operation requires that each DIT4192 operates in Mono mode, which is supported in both Software and Hard- ware control modes. In Mono mode, the DIT4192 transmits two consecutive samples of a single channel for both the Channel A and ...

PACKAGE DRAWING PW (R-PDSO-G**) 14 PINS SHOWN 0, 1,20 MAX PINS ** DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions ...

... PACKAGING INFORMATION (1) Orderable Device Status DIT4192IPW ACTIVE DIT4192IPWG4 ACTIVE DIT4192IPWR ACTIVE DIT4192IPWRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing DIT4192IPWR TSSOP PW PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 28 2000 330.0 16.4 6.9 Pack Materials-Page 1 11-Mar-2008 ...

Device Package Type DIT4192IPWR TSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 Pack Materials-Page 2 11-Mar-2008 Width (mm) Height (mm) 346.0 346.0 33.0 ...

PW (R-PDSO-G**) 14 PINS SHOWN 0, 0,15 1,20 MAX 0,05 PINS ** DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body ...

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