PCM9211PTR

Manufacturer Part NumberPCM9211PTR
DescriptionIC TXRX DGTL AUDIO 216KHZ 48LQFP
ManufacturerTexas Instruments
TypeTransceiver
PCM9211PTR datasheet
 


Specifications of PCM9211PTR

ApplicationsHome TheaterMounting TypeSurface Mount
Package / Case48-LQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-27688-2  
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216-kHz Digital Audio Interface Transceiver (DIX)
FEATURES
1
• Integrated DIX, ADC, and Signal Routing:
23456
– Asynchronous Operation (DIR, DIT, ADC)
– Mux and Routing of PCM Data:
2
– I
S™, Left-Justified, Right-Justified
– Multipurpose Input/Output Pins
Digital Audio I/F Receiver (DIR):
– 24-bit, 216-kHz Capable
– 50-ps Ultralow Jitter
– Non-PCM Detection (IEC61937, DTS-CD/LD)
– 12x S/PDIF Input Ports:
– 2x Coaxial S/PDIF Inputs
– 10x Optical S/PDIF Inputs
Digital Audio I/F Transmitter (DIT):
– 24-Bit, 216-kHz Capable
– 24-Bit Data Length
– 48-Bit Channel Status Buffer
– Synchronous/Asynchronous Operation
Analog-to-Digital Converter (ADC):
– 24-Bit, 96-kHz Capable
– Dynamic Range: 101 dB (f
– Synchronous/Asynchronous Operation
Routing Function:
– Input: 3x PCM, 1x DIR, 1x ADC
– Output: Main Out, Aux Out, DIT
– Multi-Channel (8-Ch) PCM Routing
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AC-3 is a trademark of Dolby Laboratories.
2
SPI is a trademark of Motorola, Inc.
3
2
2
I
S, I
C are trademarks of NXP Semiconductors.
4
TOSLINK is a trademark of Toshiba Corp.
5
All other trademarks are the property of their respective owners.
6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
with Stereo ADC and Routing
Check for Samples:
PCM9211
Other Function Features:
– Power Down (Pin and Register Control)
– PCM Port Sampling Frequency Counter
– GPIO and GPO
– OSC for External Crystal (24.576 MHz)
– SPI™, I
Power Supply:
– 3.3 V (2.9 V to 3.6 V) for DIX, All Digital
– 5 V (4.5 V to 5.5 V) for ADC Analog
Operating Temperature: –40°C to +85°C
Package: 48-Pin LQFP
APPLICATIONS
Home Theater and AVR Equipment
Television and Soundbars
Musical Instruments, Recording, and
Broadcast
High-Performance Soundcards
DESCRIPTION
The PCM9211 is a complete analog and digital
front-end
= 96 kHz)
S
recorders.
The PCM9211 integrates a stereo ADC, S/PDIF
transceiver with up to 12 multiplexed inputs and 3x
PCM inputs to allow other audio receivers to be
multiplexed along with the analog and S/PDIF signals
to a digital signal processor (DSP).
PCM9211
SBAS495 – JUNE 2010
2
C™ or Hardware Control Modes
for
today's
multimedia
players
Copyright © 2010, Texas Instruments Incorporated
and

PCM9211PTR Summary of contents

  • Page 1

    ... PCM inputs to allow other audio receivers to be multiplexed along with the analog and S/PDIF signals to a digital signal processor (DSP). PCM9211 SBAS495 – JUNE 2010 2 C™ or Hardware Control Modes for today's multimedia players Copyright © 2010, Texas Instruments Incorporated and ...

  • Page 2

    ... PCM9211 (1) –0 –0 –0 –0 Product Folder Link(s): PCM9211 www.ti.com (1) ORDERING TRANSPORT MEDIA, NUMBER QUANTITY PCM9211PT Tray, 250 PCM9211PTR Tape and Reel, 1000 PCM9211 UNIT –0.3 to +4.0 V –0.3 to +6.5 V ±0.1 V ±0.1 V –0.3 to +6.5 V –0.3 to +6.5 V –0.3 to +6.5 V – ...

  • Page 3

    ... RX1DIS = 0. At power down by Register 34h/RX0DIS and RX1DIS= 1 (default), RXIN0 and RXIN1 are internally tied high. (6) Pins: MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3, SCKO, BCK, LRCK, DOUT, MPO0-1, ERROR/INT0, NPCM/INT1. (7) Pin: XTO. Copyright © 2010, Texas Instruments Incorporated = V = 3.3 V, and unless otherwise noted. ...

  • Page 4

    ... MIN TYP MAX UNIT 2.9 3.3 3.6 VDC 2.9 3.3 3.6 VDC 4.5 5.0 5.5 VDC 2.9 3.3 3.6 VDC 4 150 350 150 350 110 250 mA 3.2 mA 3.2 4 135 mW 180 mW 0.85 mW –40 +85 °C 100 °C/W Copyright © 2010, Texas Instruments Incorporated ...

  • Page 5

    ... Stop band attenuation > 0.583 f Group delay time HPF frequency response –3 dB ADC, COMMON VOLTAGE OUTPUT V output voltage COM V output impedance COM Allowable V output COM source/sink current Copyright © 2010, Texas Instruments Incorporated = V = 3.3 V, and unless otherwise noted. DD DDRX CCAD TEST CONDITIONS ...

  • Page 6

    ... MHz 3.584 55.296 MHz 0.448 13.824 MHz 7 216 kHz 24.576 MHz –100 100 ppm 24.576 MHz ±5 ±5 % 0.896 55.296 MHz 0.448 13.824 MHz 7 216 kHz 0.896 55.296 MHz 0.448 13.824 MHz 7 216 kHz Copyright © 2010, Texas Instruments Incorporated ...

  • Page 7

    ... MPIO_C2 I/O Yes 10 MPIO_C3 I/O Yes 11 MPIO_B0 I/O Yes 12 MPIO_B1 I/O Yes 13 MPIO_B2 I/O Yes 14 MPIO_B3 I/O Yes 15 MPO0 O (1) Schmitt trigger input Copyright © 2010, Texas Instruments Incorporated PIN CONFIGURATIONS PT PACKAGE LQFP-48 (TOP VIEW PCM9211 PIN FUNCTIONS No DIR Error detection output / Interrupt0 output ...

  • Page 8

    ... ADC analog voltage input, left channel No ADC analog voltage input, right channel Product Folder Link(s): PCM9211 www.ti.com DESCRIPTION 2 (2) C slave address setting0 2 (2) (3) C data input/output 2 (2) C clock input 2 (2) C slave address setting1 section, Control Mode Pin Setting) (2) (2) (2) (2) (5) Copyright © 2010, Texas Instruments Incorporated ...

  • Page 9

    ... Control SPI/I C MDO /ADR 0 INTERFACE MS/ADR 1 GPIO/GPO Data RST Reset and Mode ADC MODE Set ANALOG VCCAD Copyright © 2010, Texas Instruments Incorporated FILT AUTO DIR DIR ADC PLL AUXIN0 AUXIN1 Lock :DIR AUXIN2 Unlock:ADC Clock/ Data Recovery AUTO DIR ADC ...

  • Page 10

    ... S DYNAMIC RANGE AND SNR vs TEMPERATURE Dynamic Range SNR 100 T , Free-Air Temperature ( C) ° A Figure 2. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE Dynamic Range SNR 4.75 5.00 5.25 5. Supply Voltage (V) CC Figure 4. Copyright © 2010, Texas Instruments Incorporated ...

  • Page 11

    ... Frequency (kHz) Figure 5. ADC INTERNAL FILTER DECIMATION FILTER STOP BAND CHARACTERISTIC 100 - 120 - 140 - 160 - Normalized Frequency (x f Figure 7. Copyright © 2010, Texas Instruments Incorporated = 3 kHz, SCK = 512f , and 24-bit data, unless otherwise noted 100 - 120 - 140 - PASSBAND CHARACTERISTIC 0 ...

  • Page 12

    ... Normalized Frequency (x f /1000) Figure 9. 12 Submit Documentation Feedback = 3 kHz, SCK = 512f DD S ANTIALIASING FILTER CHARACTERISTIC 0.3 0 Product Folder Link(s): PCM9211 www.ti.com , and 24-bit data, unless otherwise noted 100 Frequency (kHz) Figure 10. Copyright © 2010, Texas Instruments Incorporated ...

  • Page 13

    ... When the PLL is locked, the secondary clock source automatically selects the PLL clock (256f XTI clock source is selected. Register 32h should be used for dividing in the lock status (that is, the PLL source). When unlocked, Register 33h should be used (the XTI source). Copyright © 2010, Texas Instruments Incorporated OVERVIEW Product Folder Link(s): ...

  • Page 14

    ... Additionally, interrupts can be generated based on the ADC inputs being larger than user-defined threshold levels. In standalone mode, the ADC can be either a clock master or a clock slave. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 www.ti.com ...

  • Page 15

    ... For example, to access all 12 S/PDIF inputs, the MPIO_Ax pins can be configured to support S/PDIF RXIN8 and RXIN11. However, if the application requires an additional I for an Aux In instead of RXIN8 and RXIN11. Copyright © 2010, Texas Instruments Incorporated 2 S protocol. Each I/O can support SCK (system clock), BCK ...

  • Page 16

    ... Submit Documentation Feedback PCM9211 MODULE DESCRIPTIONS for an illustration of the timing sequence during an internal power-on reset exceeds 2.2 V (typ 2.2 V typ DD Tied DGND DD t RSTL Product Folder Link(s): PCM9211 www.ti.com directly. An external pull-up DD Figure 11 3.3 V typ DD Copyright © 2010, Texas Instruments Incorporated ...

  • Page 17

    ... All formats are provided twos complement, MSB first. They are selectable through SPI-/I The specific control registers are: • DIR: RXFMT[2:0] • ADC: ADFMT[1:0] • DIT: TXFMT[1:0] Copyright © 2010, Texas Instruments Incorporated DESCRIPTION MIN 1 Table PIN NAME SCKO BCK LRCK ...

  • Page 18

    ... LSB MSB LSB MSB Left-channel LSB MSB LSB MSB Left-channel LSB LSB Left-channel LSB LSB Product Folder Link(s): PCM9211 www.ti.com Right-channel LSB Right-channel LSB LSB Right-channel MSB LSB MSB LSB Right-channel MSB LSB MSB LSB Copyright © 2010, Texas Instruments Incorporated 1 1 ...

  • Page 19

    ... SCL System clock duty cycle Note: This timing requirement is applied when ADC clock source (Register 42h/ADCLK) is AUXIN0, AUXIN1 or AUXIN2. Figure 13. ADC System Clock Input Timing Copyright © 2010, Texas Instruments Incorporated or 512f S for common audio sampling rates. SCK Table 3. ADC Clock Requirements ...

  • Page 20

    ... SCK source (such as a DSP or PLL circuit), and provide BCK and LRCK to the rest of the PCM9211 circuitry and external components. To configure the ADC for standalone operation, set MPCSEL[2:0] to 001. ADIFMD should also be set to 010 or 100. 20 Submit Documentation Feedback or 512f . S S Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 21

    ... ADDIS Internal Normal Operation Reset DOUT Figure 14. ADC Output at Power Up and Power Down Copyright © 2010, Texas Instruments Incorporated – 215), where AT1x[7:0] DEC after the internal reset is released. DOUT then starts to output data = 1936/f from the start of fade-in. If synchronization is not ...

  • Page 22

    ... Serial Control Mode section. The default mode is slave mode. Master . DOUT changes on the falling edge of BCK. The default timing LRH LRS t DOD DESCRIPTION Product Folder Link(s): PCM9211 www.ti.com 1.4 V 1 MIN TYP MAX UNITS Copyright © 2010, Texas Instruments Incorporated ...

  • Page 23

    ... Changes or drift less than ±5 BCKs do not cause any issues with the device. output when synchronization is lost. The ADC output, DOUT, maintains its previous state if the system clock stops. Copyright © 2010, Texas Instruments Incorporated . DOUT changes on the falling edge of BCK. The detailed S 16 ...

  • Page 24

    ... The ADC also integrates CC PP (pin 44) is brought out for decoupling purposes. This pin is COM (nominal), and is used as internal reference voltage for the CCAD . S Product Folder Link(s): PCM9211 www.ti.com 3 Normal L and V R. These are single-ended Copyright © 2010, Texas Instruments Incorporated ...

  • Page 25

    ... The flag is cleared when Register 2Dh is read. VINL VINR LVL DET Flag NPCM/INT1 pin Register 2Dh_B0 2 SPI/I C Figure 19. Operation of the ADC Level Detect Circuitry Copyright © 2010, Texas Instruments Incorporated Figure MainPort/MPIO Matrix Level INT Detector ADDTLV[1:0] ERROR/ ...

  • Page 26

    ... PCM9211 itself. For differential inputs (such as the AES/EBU standard), differential to single-ended circuitry is required. 26 Submit Documentation Feedback MPIO Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 www.ti.com . They can also be PP section) ...

  • Page 27

    ... MHz 24 kHz 32 kHz 44.1 kHz 2.8224 MHz 48 kHz 64 kHz 88.2 kHz 5.6448 MHz 96 kHz 128 kHz 176.4 kHz 11.2896 MHz 192 kHz 12.288 MHz Copyright © 2010, Texas Instruments Incorporated , 256f or 512f . PSCK[2:0] SETTING LRCKO PSCK2 ...

  • Page 28

    ... Metal film or carbon 0.068 µF Film or ceramic (CH or C0G) 0.0047 µF Film or ceramic (CH or C0G) and C and the current limiting resistor Product Folder Link(s): PCM9211 www.ti.com Figure 20 DGND TOLERANCE ≤ 5% ≤ 5% ≤ 5% all depend on the d Copyright © 2010, Texas Instruments Incorporated and ...

  • Page 29

    ... Table 7. DIR Serial Audio Data Output Format Set by RXFMT[2:0] DIR SERIAL AUDIO DATA OUTPUT FORMAT 24-bit MSB First, Right-Justified 16-bit MSB First, Right-Justified 24-bit MSB First, I 24-bit MSB First, Left-Justified Copyright © 2010, Texas Instruments Incorporated Crystal OSC 24.576 MHz Circuit Internal Clock ...

  • Page 30

    ... Figure 23. DIR Decoded Audio Data Output Timing 30 Submit Documentation Feedback 17±1BCK t SCY t BCL t BCY BCDO DESCRIPTION Product Folder Link(s): PCM9211 www.ti.com Figure 23 illustrates the MIN TYP MAX UNITS 4 CKLR MIN TYP MAX UNITS 18 ns – 1/64f – Copyright © 2010, Texas Instruments Incorporated ...

  • Page 31

    ... Figure 24. LRCKO, DOUT, BFRAME, COUT, UOUT, and VOUT Output Timing The RXVDLY Register in Register 22h controls when the VOUT pin goes high (either immediately the start of the sample/frame). Figure 25 shows these timing sequences. DOUT VOUT (RXVDLY = 1) VOUT (RXVDLY = 0) Copyright © 2010, Texas Instruments Incorporated MPIO Figure 24. Figure C0L ...

  • Page 32

    ... Interpolation processing by previous data Parity error n+1 n+1 n+2 Parity error OPTIONS DIR Error (default), INT0 or Hi-Z DIR NPCM (default), INT1 or Hi-Z Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 www.ti.com n+2 n+3 n n+2 n+3 n+3 Calculator Complete) ...

  • Page 33

    ... INT0/1 Register f Calculator S Complete DIR ‘1’ Figure 28. Error Output and Interrupt Output Block Diagram Copyright © 2010, Texas Instruments Incorporated Calculator Complete), INT0 or INT1 performs a bitwise evaluation S Interrupt Source To INTx Mask Bit Figure 27. DIR Interrupt Mask Logic Figure Product Folder Link(s): ...

  • Page 34

    ... Once the XTI source clock is S restored, the f calculator resumes operation. S Register 39h/SFSST indicates the calculator status. Before reading SFSOUT[3:0 recommended that the user verify that the SFSST status is '0'. 34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 www.ti.com ...

  • Page 35

    ... Register 21h/RXFSRNG is used for global control of the acceptable sampling frequencies. If normal mode is selected, the range of acceptable sampling frequency is restricted from 28 kHz to 108 kHz. If wide mode is selected, the range is from 7 kHz to 216 kHz. Copyright © 2010, Texas Instruments Incorporated CALCULATED SAMPLING FREQUENCY OUTPUT SFSOUT3 ...

  • Page 36

    ... PFSTGT[2:0] 000 ADC 001 010 011 Sampling Frequency 100 101 110 DIT 111 is decoded to 4-bit data and stored in the PFSOUT[3:0] register. The input S Product Folder Link(s): PCM9211 www.ti.com Figure 29 illustrates the sampling Audio Port Calculator Copyright © 2010, Texas Instruments Incorporated ...

  • Page 37

    ... Copyright © 2010, Texas Instruments Incorporated given in Table 9) are any clock rate within ±2%. The relation S range is shown in Table 9 ...

  • Page 38

    ... DIR Source can be configured using Register 23h/ERRWT[1:0]. t can be configured using Register XTIWT Interrupts; configured by Register 25h) Product Folder Link(s): PCM9211 www.ti.com Non-Biphase Unlock t CLKST2 t XTIWT XTI (ADC) Source MUTE ADC Source . During that CLKST1 is 50 ms, CLKST2 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 39

    ... The following sequence is an example of reading P function. 1. Set Register 2Ah/MPCRNW0 to '0'. 2. Check that Register 2Ch/OPCRNW0 is '1'. 3. Read the P and P buffers Copyright © 2010, Texas Instruments Incorporated AUTO select signal defined by REG.25h excluding AERROR. ERROR defined by REG.25h SCK/BCK/LRCK/DOUT REG.26h/AERROR REG.42h/ADCKOUT REG.26h/ACKSL SCK/BCK/LRCK or P ...

  • Page 40

    ... SCK 256f 512f S S 4.096 MHz 5.6448 MHz 6.144 MHz 8.192 MHz 11.2896 MHz 12.288 MHz 16.384 MHz 22.5792 MHz 24.576 MHz 32.768 MHz 45.1584 MHz 49.152 MHz N/A N/A N/A Copyright © 2010, Texas Instruments Incorporated ...

  • Page 41

    ... Register 6Fh/MPCSEL[2:0] to '101'. This configuration then bypasses the standard DIT connections through the device and connects them directly to MPIO_C. Channel Status and Validity flags continue to be sourced from the same registers as they would during normal DIT operation. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 PCM9211 SBAS495 – ...

  • Page 42

    ... AVR Application2: Secondary BCK/LRCK Output, XTI buffered Output, Interrupt Output GPIO (General Purpose I/O), Logical high or low I/O, selectable I/O direction for each pin Hi-Z status, selectable for each pin Product Folder Link(s): PCM9211 www.ti.com Flag S Copyright © 2010, Texas Instruments Incorporated ...

  • Page 43

    ... OUT 10 OUT 11 IN/ OUT (1) MPIO_A0 to MPIO_A3 are set to Hi-Z by the MPA0HZ to MPA3HZ registers as default. Copyright © 2010, Texas Instruments Incorporated Flag section) NOTE MPIO GROUP A FUNCTION Biphase input (RXIN8/RXIN9/RXIN10/RXIN11) AVR Application 1 (CLKST, VOUT, XMCKO, INT0) (default) AVR Application 2 (SBCK, SLRCK, XMCKO, INT0) ...

  • Page 44

    ... AUXIN1 (ASCKI1/ABCKI1/ALRCKI1/ADIN1) (default) ADC Standalone, clock, and data (ADSCK/ADBCK/ADLRCK/ADDOUT) Sampling frequency calculated result output, SFSOUT[3:0] DIR Flags output or GPIO DIR BCUV output (BFRAME/COUT/UOUT/VOUT) DIT Standalone, clock, and data (TXSCK/TXBCK/TXLRCK/TXDIN) Reserved Reserved Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 45

    ... OUT 1011 OUT 1100 OUT 1101 OUT 1110 OUT 1111 OUT Copyright © 2010, Texas Instruments Incorporated Table 15. MPO0 Pin MPO0 FUNCTION Hi-Z GPO0, Output data = Logic high level GPO0, Output data = Logic low level VOUT INT0 INT1 CLKST EMPH BPSYNC ...

  • Page 46

    ... Independent biphase selector 0, output0 Independent biphase selector 1, output1 Built-in DIT, biphase output Table 22. AUX Clocks Output DESCRIPTION Secondary bit clock output Secondary LR clock output XTI pin input clock buffered output Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 47

    ... GPIC0 MPIO_C0 GPIC1 MPIO_C1 GPIC2 MPIO_C2 GPIC3 MPIO_C3 Copyright © 2010, Texas Instruments Incorporated Table 23. Audio Clock and Data I/O DESCRIPTION AUXIN1, system clock input AUXIN1, bit clock input AUXIN1, LR clock input AUXIN1, data input AUXIN2, system clock input AUXIN2, bit clock input ...

  • Page 48

    ... SFSOUT0 (1) (1) DIR Flag / GPIO UOUT VOUT EALRCKO EADIN Reserved Reserved Test Mode Test Mode MPIO_C2 MPIO_C3 ALRCKI1 ADIN1 ADLRCK ADDOUT SFSOUT1 SFSOUT0 (1) (1) DIR Flag / GPIO UOUT VOUT TXLRCK TXDIN Reserved Reserved Reserved Reserved Copyright © 2010, Texas Instruments Incorporated ...

  • Page 49

    ... RXIN2. When the DIR is unlocked, the ADC has priority, and uses the Main port. When the DIR is locked, data from the MAIN PORT are DIR data. Copyright © 2010, Texas Instruments Incorporated Figure 32. MPIO_A0-A3 are selected by CLKST, VOUT, XMCKO, and ...

  • Page 50

    ... AUTO DIR ADC AUXIN0 AUXIN1 NOTE Product Folder Link(s): PCM9211 www.ti.com SCKO BCK MAIN OUTPUT LRCK PORT DOUT DIT MPO 0 MPO0/1 MPO 1 SELECTOR MPIO_ B0 (MDOUT 0) MPIO_ B1 (MDOUT 1) AUXOUT MPIO _B MPIO_ B2 (MDOUT 2) SELECTOR AUXIN 2 MPIO_ B3 (MDOUT 3) Copyright © 2010, Texas Instruments Incorporated ...

  • Page 51

    ... DSDLI MPIO_B3 DSCKO SCKO DBCKO BCK DSDRO LRCK DSDLO DOUT DBCK DSDRI DSDLI Copyright © 2010, Texas Instruments Incorporated MCHRSRC '00' or '10' (1) MAIN OUT (1) MAIN OUT (1) MAIN OUT Logic low Logic low Logic low DIR section of this data sheet. It can either be the DIR Figure 34 illustrates the DSD format ...

  • Page 52

    ... TXDSD = Enable 6Bh = 14h MOSSRC = DIR MOPSRC = AUXIN1 DESCRIPTIONS 34h = CFh RXSEL = TXOUT 60h = 55h TXSSRC = AUXIN2 TXPSRC = AUXIN2 61h = 14h TXDSD = Enable 6Bh = 14h MOSSRC = DIR MOPSRC = AUXIN1 Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 53

    ... MPIO_ C MPIO _C2( DSDRI ) SELECTOR AUXIN1 MPIO _C3( DSDLI ) Note: Blue lines are through-paths for DBCKI, DSDRI, and DSDLI. Figure 35. DSD Input Mode Block Diagram Copyright © 2010, Texas Instruments Incorporated FILT AUTO DIR DIR ADC PLL AUXIN0 AUXIN1 Lock :DIR ...

  • Page 54

    ... Two-wire (I Four-wire (SPI) serial control 2 C Control Interfaces DEFINITION SPI MODE MDO MDI Address Product Folder Link(s): PCM9211 www.ti.com 2 C) serial control MODE ADR0 SDA SCL ADR1 Figure 36 shows the control data LSB Register Data Copyright © 2010, Texas Instruments Incorporated ...

  • Page 55

    ... MDO remains in a Hi-Z (or high impedance) state except for a period of eight MC clocks for actual data transfer MDI DC “1 ” ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 MDO “ ” Copyright © 2010, Texas Instruments Incorporated Figure 37. Register Write Operation after the start of the block. However, once ADR 0 DON ’ ...

  • Page 56

    ... Submit Documentation Feedback MCH MCL t MCY t t MDS MDH LSB (D0 MSB (D7) LSB (D0 ) DESCRIPTION specification 2. ADR1 Product Folder Link(s): PCM9211 www.ti.com t MHH 1 1 MDR 0.5*V DD MIN MAX UNITS 100 MCY LSB ADR0 R/W Copyright © 2010, Texas Instruments Incorporated ...

  • Page 57

    ... M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition W: Write R: Read ACK: Acknowledge NACK: Not Acknowledge Sp: Stop Condition Note: The slave address after the repeated start condition must be the same as the previous slave address. Figure 42. Framework for Read Operation Copyright © 2010, Texas Instruments Incorporated 40 – – ...

  • Page 58

    ... MAX UNITS 400 kHz 1.3 µs 1.3 µs 0.6 µs 0.6 µs 0.6 µs 100 ns 0 900 0.1C 300 0.1C 300 0.1C 300 0.1C 300 ns B 0.6 µs n 100 pF 0.2 × 0.1 × 0.05 × Copyright © 2010, Texas Instruments Incorporated ...

  • Page 59

    ... C8, C9: OSC load capacitor; generally, a 10-pF to 30-pF capacitor is used, but it depends on the crystal resonator and PCB layout. C10, C11: DC blocking capacitor for coax input, 0.1 mF. X1: Crystal resonator. Use a 24.576-MHz fundamental resonator when the XTI clock source is needed. Copyright © 2010, Texas Instruments Incorporated APPLICATION INFORMATION + ...

  • Page 60

    ... Example of C and R values with gain (G) and corner frequency ( kΩ kΩ kΩ 330 0 0 kHz C Figure 45 Submit Documentation Feedback biased buffering for 2-V input with overvoltage protection. RMS Biased Buffering Example COM Product Folder Link(s): PCM9211 www.ti.com +V +5V Output - V VCOM 0V Copyright © 2010, Texas Instruments Incorporated ...

  • Page 61

    ... DIT Function Control 3/3 63h DIT Channel Status Data Buffer 1/6 64h DIT Channel Status Data Buffer 2/6 65h DIT Channel Status Data Buffer 3/6 66h DIT Channel Status Data Buffer 4/6 Copyright © 2010, Texas Instruments Incorporated REGISTER INFORMATION Table 35. REGISTER MAP R R/W ...

  • Page 62

    ... MPC2FLG2 MPC2FLG1 MPB2FLG0 MPO0SEL3 MPO0SEL2 MPO0SEL1 MPO0SEL0 GIOA3DIR GIOA2DIR GIOA1DIR GIOA0DIR RSV GIOC3DIR GIOC2DIR GIOC1DIR GIOC0DIR GPOA3 GPOA2 GPOA1 GPOA0 RSV GPOC3 GPOC2 GPOC1 GPOC0 GPIB0 GPIA3 GPIA2 GPIA1 GPIA0 RSV GPIC3 GPIC2 GPIC1 GPIC0 Copyright © 2010, Texas Instruments Incorporated B0 ...

  • Page 63

    ... NOTE: ERRSEL must be '0' when Register 26h/AERROR = 1 or Register 42h/ADFSLMT = the signal CLKST is used. NPCMHZ: NPCM/INT1 Port Output Hi-Z Control 0: Output (default) 1: Hi-Z NPCMSEL: NPCM/INT1 Port Output Source Select 0: NPCM (default) 1: INT1 spacer Copyright © 2010, Texas Instruments Incorporated NOTE (Address: 20h, Write and Read MCHR RSV ERRHZ ...

  • Page 64

    ... Register 21h, DIR Initial Settings 1/3 (Address: 21h, Write and Read RSV RXFSRNG RSV Register 22h, DIR Initial Settings 2/3 (Address: 22h, Write and Read RSV CLKSTP RSV Product Folder Link(s): PCM9211 www.ti.com RSV RSV RSV RSV RSV RXVDLY Copyright © 2010, Texas Instruments Incorporated ...

  • Page 65

    ... ERROR Release after three counts of preamble B These counts are only available when DIR is unlocked or DIR sampling frequency is changed or exceeds limits defined by DIR Acceptable f CLKST also uses ERRWT to release. Copyright © 2010, Texas Instruments Incorporated Register 23h, DIR Initial Settings 3/3 (Address: 23h, Write and Read) B5 ...

  • Page 66

    ... XMCKDIV[1:0]: XMCKO (XTI Clock Buffered Output) Output Clock Dividing Ratio 00: XTI/1 (24.576 MHz) (default) 01: XTI/2 (12.288 MHz) 10: XTI/4 (6.144 MHz) 11: XTI/8 (3.072 MHz) 66 Submit Documentation Feedback (Address: 24h, Write and Read RSV XMCKEN XMCKDIV1 Product Folder Link(s): PCM9211 www.ti.com XMCKDIV0 RSV RSV Copyright © 2010, Texas Instruments Incorporated ...

  • Page 67

    ... EUNLOCK: PLL Lock Error 0: Not selected 1: Selected (default) This register is used for setting the ERROR output factor. The required factors of ERROR set to '1' are selected based on OR logic. Copyright © 2010, Texas Instruments Incorporated Register 25h, ERROR Cause Setting (Address: 25h, Write and Read ...

  • Page 68

    ... AVALID: Validity Flag 0: Not selected (default) 1: Selected AUNLOCK: PLL Lock Error 0: Not selected 1: Selected (default) 68 Submit Documentation Feedback (Address: 26h, Write and Read RSV AFSLMT ANPCM Product Folder Link(s): PCM9211 www.ti.com AVALID RSV AUNLOCK Limit Setting Register. S Copyright © 2010, Texas Instruments Incorporated ...

  • Page 69

    ... S 10 kHz S 11 kHz S This condition of receivable sampling frequency is used as the ERROR and AUTO source selection when EFSLMT or AFSLMT is set to '1'. Copyright © 2010, Texas Instruments Incorporated Range Setting and Mask S (Address: 27h, Write and Read RSV NOMLMT HILMT1 ...

  • Page 70

    ... DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs. 70 Submit Documentation Feedback Register 28h, Non-PCM Definition (Address: 28h, Write and Read CS1BPLS NPCMP RSV Detection NOTE Product Folder Link(s): PCM9211 www.ti.com DTSCD PAPB CSBIT1 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 71

    ... One period 10: Two periods 11: Four periods The DTSCD Register (Register 28h) must be '1' (that is, selected) in order to output the DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs. Copyright © 2010, Texas Instruments Incorporated (Address: 29h, Write and Read ...

  • Page 72

    ... C 0: Not masked 1: Masked (default) MFSCHG0: Renewal Flag of f Calculator Result S 0: Not masked 1: Masked (default) 72 Submit Documentation Feedback (Address: 2Ah, Write and Read MEMPHF0 MDTSCD0 MCSRNW0 Product Folder Link(s): PCM9211 www.ti.com MPCRNW0 MFSCHG0 RSV Copyright © 2010, Texas Instruments Incorporated ...

  • Page 73

    ... C 0: Not masked 1: Masked (default) MFSCHG1: Renewal Flag of f Calculator Result S 0: Not masked 1: Masked (default) MADLVL1: ADC Input Level Detection Status 0: Not masked 1: Masked (default) Copyright © 2010, Texas Instruments Incorporated (Address: 2Bh, Write and Read MEMPHF1 MDTSCD1 MCSRNW1 Product Folder Link(s): ...

  • Page 74

    ... When this register is read, the INT0 output is cleared. 74 Submit Documentation Feedback Register 2Ch, INT0 Output Register (Address: 2Ch, Read-Only OEMPHF0 ODTSCD0 OCSRNW0 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com OPCRNW0 OFSCHG0 RSV N/A N/A 0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 75

    ... Not detect the defined threshold input level 1: Detect the defined threshold input level NOTE: The threshold input level is defined by Register 2Eh, ADLVLTH[1:0]. When this register is read, the INT1 output is cleared. Copyright © 2010, Texas Instruments Incorporated Register 2Dh, INT1 Output Register (Address: 2Dh, Read-Only) B5 ...

  • Page 76

    ... Submit Documentation Feedback (Address: 2Eh, Write and Read RSV ADLVLTH1 ADLVLTH0 Register 2Fh, DIR Output Data Format (Address: 2Fh, Write and Read RSV RSV RSV Product Folder Link(s): PCM9211 www.ti.com INT0P RSV RSV RXFMT2 RXFMT1 RXFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 77

    ... PSCK[2:0]: DIR Recovered Clock Frequency Setting 000: 128f S 001: Reserved 010: 256f (default) S 011: Reserved 100: 512f S 101: Reserved 110: Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated (Address: 30h, Write and Read RSV PSCKAUTO RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – ...

  • Page 78

    ... Submit Documentation Feedback (Address: 31h, Write and Read XSCK1 XSCK0 XBCK1 NOTE Product Folder Link(s): PCM9211 www.ti.com XBCK0 XLRCK1 XLRCK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 79

    ... S 010: f (1x LRCK) (default) S 011: 2f (2x LRCK) S 100: 4f (4x LRCK) S 101: Reserved 110: Reserved 111: Reserved spacer Copyright © 2010, Texas Instruments Incorporated (Address: 32h, Write and Read PSBCK1 PSBCK0 RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ...

  • Page 80

    ... XTI/512 (48 kHz) (default) 011: XTI/1024 (24 kHz) 100: XTI/2048 (12 kHz) 101: Reserved 110: Reserved 111: Reserved 80 Submit Documentation Feedback (Address: 33h, Write and Read XSBCK1 XSBCK0 RSV Product Folder Link(s): PCM9211 www.ti.com XSLRCK2 XSLRCK1 XSLRCK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 81

    ... Reserved 1110: Reserved 1111: TXOUT (internal DIT output) RX0DIS or RX1DIS must be set to '0', even when an S/PDIF, TTL, or OPTICAL input is provided into RXIN0 or RXIN1, without use of the built-in COAX amplifier. Copyright © 2010, Texas Instruments Incorporated (Address: 34h, Write and Read ...

  • Page 82

    ... Reserved 1111: TXOUT (internal DIT output) MPO0MUT: MPO0 Mute Control 0: Output (default) 1: MUTE (Logic low level) 82 Submit Documentation Feedback (Address: 35h, Write and Read RSV MPO0MUT RO0SEL3 Product Folder Link(s): PCM9211 www.ti.com RO0SEL2 RO0SEL1 RO0SEL0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 83

    ... PFSTGT[2:0]: Port f Calculator, Target Port Setting S 000: DIR (default) 001: ADC 010: AUXIN0 011: AUXIN1 100: AUXIN2 101: Main output port 110: AUX output port 111: DIT Copyright © 2010, Texas Instruments Incorporated (Address: 36h, Write and Read RSV MPO1MUT RO1SEL3 ...

  • Page 84

    ... Calculating and PFSOUT indicates the previous value when no source comes to the port that is selected by Register 37h/PFSTGT. 84 Submit Documentation Feedback (Address: 38h, Read-Only PFSPO1 PFSPO0 PFSOUT3 N/A N/A N/A NOTE Product Folder Link(s): PCM9211 www.ti.com PFSOUT2 PFSOUT1 PFSOUT0 N/A N/A N/A Copyright © 2010, Texas Instruments Incorporated ...

  • Page 85

    ... SFSST and SFSOUT always output the status when these registers are read. The other registers do not have clear functions when these are read. To enable these registers, DIR must be powered on (Register 40h/RXDIS = 0). Copyright © 2010, Texas Instruments Incorporated (Address: 39h, Read-Only) B5 ...

  • Page 86

    ... B4 B3 PC5 PC4 PC3 N/A N/A N/A Address: 3Bh, Read-Only PC13 PC12 PC11 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com PC2 PC1 PC0 N/A N/A N PC10 PC9 PC8 N/A N/A N/A /P [15:0] is not C D Copyright © 2010, Texas Instruments Incorporated ...

  • Page 87

    ... Normal operation (default) 1: Power down TXDIS: Power Down for DIT 0: Normal operation (default) 1: Power down XODIS: Power Down for OSC 0: Normal operation (default) 1: Power down XODIS is superior to OSCAUTO. Copyright © 2010, Texas Instruments Incorporated Buffer (Burst Preamble Address: 3Ch, Read-Only PD5 ...

  • Page 88

    ... SCK/BCK/LRCK dividers). Its frequency is set by the register of XSCK[1:0], XBCK[1:0], and XLRCK[1:0].). 88 Submit Documentation Feedback Register 42h, ADC Function Control 1/3 (Address: 42h, Write and Read ADCKOUT ADDTRX7 ADFSLMT Product Folder Link(s): PCM9211 www.ti.com ADCLK2 ADCLK1 ADCLK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 89

    ... Default Value 1 1 Memo ADATTR[7:0]: ADC R-Ch, Digital ATT Setting 1111 1111: +20.0 dB 1111 1110: +19.5 dB 1101 0111 (default) 1101 0110: –0.5 dB 0000 1111: –100 dB Others: Mute Copyright © 2010, Texas Instruments Incorporated (Address: 46h, Write and Read ADATTL5 ADATTL4 ADATTL3 ...

  • Page 90

    ... I S (default) 01: 24-bit left-justified 10: 24-bit right-justified 11: 16-bit right-justified 90 Submit Documentation Feedback Register 48h, ADC Function Control 2/3 (Address: 48h, Write and Read ADIFMD1 ADIFMD0 RSV Product Folder Link(s): PCM9211 www.ti.com RSV ADFMT1 ADFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 91

    ... Mute disabled (default) 1: Mute enabled The mute bits, ADMUTL and ADMUTR, are used to enable or disenable the soft mute function for the corresponding ADC outputs, DOUT. Copyright © 2010, Texas Instruments Incorporated Register 49h, ADC Function Control 3/3 (Address: 49h, Write and Read) B5 ...

  • Page 92

    ... RXCS1 RXCS0 CS Bit2 CS Bit1 CS Bit0 RXCS10 RXCS9 RXCS8 CS Bit10 CS Bit9 CS Bit8 RXCS18 RXCS17 RXCS16 CS Bit18 CS Bit17 CS Bit16 RXCS26 RXCS25 RXCS24 CS Bit26 CS Bit25 CS Bit24X RXCS34 RXCS33 RXCS32 CS Bit34 CS Bit33 CS Bit32 RXCS42 RXCS41 RXCS40 CS Bit42 CS Bit41 CS Bit40 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 93

    ... DIR/ADC Automatic (DIR lock = DIR, DIR unlock = ADC) 001: DIR 010: ADC 011: AUXIN0 100: AUXIN1 (default) 100: AUXIN2 110: Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated Register 60h, DIT Function Control 1/3 (Address: 60h, Write and Read TXSSRC1 TXSSRC0 ...

  • Page 94

    ... Submit Documentation Feedback Register 61h, DIT Function Control 2/3 (Address: 61h, Write and Read TXSCK1 TXSCK0 RSV NOTE ), MPIO_B2 for L-ch data, and S Product Folder Link(s): PCM9211 www.ti.com TXDSD TXFMT1 TXFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 95

    ... The data in this register are used for both channels (L-ch and R-ch). When these register data are used for the DIT channel status data, a channel status data of bit 48 or later is all '0'. All initial values of this register are all '0'. Copyright © 2010, Texas Instruments Incorporated Register 62h, DIT Function Control 3/3 ...

  • Page 96

    ... Mute (the affected signals are selected by Register 6Ah, MOLRMTEN) Data mutes are done in synchronization with a LRCK edge. 96 Submit Documentation Feedback (Address: 6Ah, Write and Read RSV RSV AOLRMTEN Product Folder Link(s): PCM9211 www.ti.com AODMUT MOLRMTEN MODMUT Copyright © 2010, Texas Instruments Incorporated ...

  • Page 97

    ... To clean the clock jitter of the HDMI receiver output, the HDMI receiver S/PDIF output is connected with the PCM9211 S/PDIF input, and the HDMI receiver I (BCK/LRCK/DATA) are connected with the PCM9211 PCM input port. Copyright © 2010, Texas Instruments Incorporated (Address: 6Bh, Write and Read) B5 ...

  • Page 98

    ... S/PDIF output is connected to the PCM9211 S/PDIF input, and the HDMI receiver I (BCK/LRCK/DATA) are connected with the PCM9211 PCM input port. 98 Submit Documentation Feedback (Address: 6Ch, Write and Read AOSSRC1 AOSSRC0 RSV Product Folder Link(s): PCM9211 www.ti.com AOPSRC2 AOPSRC1 AOPSRC0 outputs Copyright © 2010, Texas Instruments Incorporated ...

  • Page 99

    ... BCKHZ: Main Output Port, BCKO Hi-Z Control 0: Output (default) 1: Hi-Z LRCKHZ: Main Output Port, LRCKO Hi-Z Control 0: Output (default) 1: Hi-Z DOUTHZ: Main Output Port, DOUT Hi-Z Control 0: Output (default) 1: Hi-Z Copyright © 2010, Texas Instruments Incorporated (Address: 6Dh, Write and Read MPB1HZ MPB0HZ SCKOHZ 0 ...

  • Page 100

    ... In multi-channel PCM mode, the MCHR and MPAxHz registers (20h) must be set to '0' to get the outputs from the main port. 100 Submit Documentation Feedback (Address: 6Eh, Write and Read MPC1HZ MPC0HZ MPA3HZ NOTE Product Folder Link(s): PCM9211 www.ti.com MPA2HZ MPA1HZ MPA0HZ Copyright © 2010, Texas Instruments Incorporated ...

  • Page 101

    ... Sampling Frequency Calculated Result: FSOUT[3:0] 011: DIR Flags Output or GPIO (Selected by MPC3SEL, MPC2SEL, MPC1SEL, MPC0SEL) 100: DIR BCUV OUT, BFRAME/VOUT/UOUT/COUT 101: DIT Standalone Operation, Clock, and Data I/O, TXSCK/TXBCK/TXLRCK/TXDIN 110: Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated (Address: 6Fh, Write and Read MPBSEL2 ...

  • Page 102

    ... MPA0SEL: MPIO_A0 Pin Function, DIR Flags or GPIO Select 0: DIR Flags, set by MPA0FLG[3:0] (default) 1: GPIO, set by GIOA0DIR/GPOA0/GPIA0 102 Submit Documentation Feedback (Address: 70h, Write and Read MCHRSRC1 MCHRSRC0 MPA3SEL Product Folder Link(s): PCM9211 www.ti.com MPA2SEL MPA1SEL MPA0SEL Copyright © 2010, Texas Instruments Incorporated ...

  • Page 103

    ... MPC1SEL: MPIO_C1 Pin Function, DIR Flags or GPIO Select 0: DIR Flags, set by MPC1FLG[3:0] (default) 1: GPIO, set by GIOC1DIR/GPOC1/GPIC1 MPC0SEL: MPIO_C0 Pin Function, DIR Flags or GPIO Select 0: DIR Flags, set by MPC0FLG[3:0] (default) 1: GPIO, set by GIOC0DIR/GPOC0/GPIC0 Copyright © 2010, Texas Instruments Incorporated (Address: 71h, Write and Read MPB1SEL ...

  • Page 104

    ... FSOUT3 1110: INT0 1111: INT1 These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'. 104 Submit Documentation Feedback (Address: 72h, Write and Read MPA1FLG1 MPA1FLG0 MPA0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPA0FLG2 MPA0FLG1 MPA0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 105

    ... UOUT 1000: COUT 1001: BFRAME 1010: FSOUT0 1011: FSOUT1 1100: FSOUT2 1101: FSOUT3 1110: INT0 1111: INT1 These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 73h, Write and Read MPA3FLG1 MPA3FLG0 MPA2FLG3 0 0 ...

  • Page 106

    ... INT0 1111: INT1 These register settings are effective only at MPBSEL[2:0] = '011', MPB1SEL = '0', and MPB0SEL = '0'. 106 Submit Documentation Feedback (Address: 74h, Write and Read MPB1FLG1 MPB1FLG0 MPB0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPB0FLG2 MPB0FLG1 MPB0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 107

    ... COUT 1001: BFRAME 1010: FSOUT0 1011: FSOUT1 1100: FSOUT2 1101: FSOUT3 1110: INT0 1111: INT1 These register settings are effective only at MPBSEL[2:0] = '011', MPB3SEL = '0', and MPB2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 75h, Write and Read MPB3FLG1 MPB3FLG0 MPB2FLG3 0 ...

  • Page 108

    ... INT0 1111: INT1 These register settings are effective only at MPCSEL[2:0] = '011', MPC1SEL = '0', and MPC0SEL = '0'. 108 Submit Documentation Feedback (Address: 76h, Write and Read MPC1FLG1 MPC1FLG0 MPC0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPC0FLG2 MPC0FLG1 MPC0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 109

    ... COUT 1001: BFRAME 1010: FSOUT0 1011: FSOUT1 1100: FSOUT2 1101: FSOUT3 1110: INT0 1111: INT1 These register settings are effective only at MPCSEL[2:0] = '011', MPC3SEL = '0', and MPC2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 77h, Write and Read MPC3FLG1 MPC3FLG0 MPC2FLG3 0 ...

  • Page 110

    ... DTSCD 1010: PARITY 1011: LOCK 1100: XMCKO 1101: TXOUT (default) 1110: RECOUT0 1111: RECOUT1 110 Submit Documentation Feedback (Address: 78h, Write and Read MPO1SEL1 MPO1SEL0 MPO0SEL3 Product Folder Link(s): PCM9211 www.ti.com MPO0SEL2 MPO0SEL1 MPO0SEL0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 111

    ... Input (default) 1: Output GIOA0DIR: MPIO_A0 Pin Function, GPIO I/O Direction Control 0: Input (default) 1: Output These registers are effective only at MPIO_A and MPIO_B assigned as GPIO. I/O direction setting is available by pin. Copyright © 2010, Texas Instruments Incorporated (Address: 79h, Write and Read GIOB1DIR GIOB0DIR ...

  • Page 112

    ... Input (default) 1: Output These registers are effective only at MPIO_C assigned as GPIO. I/O direction setting is available by pin. 112 Submit Documentation Feedback (Address: 7Ah, Write and Read RSV RSV GIOC3DIR Product Folder Link(s): PCM9211 www.ti.com GIOC2DIR GIOC1DIR GIOC0DIR Copyright © 2010, Texas Instruments Incorporated ...

  • Page 113

    ... Output low level (default) 1: Output high level GPOA0: MPIO_A0 Pin, GPIO Output Data Setting 0: Output low level (default) 1: Output high level These registers are effective only as GPIOs are assigned to output. Copyright © 2010, Texas Instruments Incorporated (Address: 7Bh, Write and Read GPOB1 ...

  • Page 114

    ... Output low level (default) 1: Output high level These registers are effective only as GPIOs are assigned to output. 114 Submit Documentation Feedback (Address: 7Ch, Write and Read RSV RSV GPOC3 Product Folder Link(s): PCM9211 www.ti.com GPOC2 GPOC1 GPOC0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 115

    ... Detect low level 1: Detect high level GPIA1: MPIO_A1 Pin, GPIO Input Data 0: Detect low level 1: Detect high level GPIA0: MPIO_A0 Pin, GPIO Input Data 0: Detect low level 1: Detect high level Copyright © 2010, Texas Instruments Incorporated (Address: 7Dh, Read-Only GPIB1 GPIB0 GPIA3 ...

  • Page 116

    ... GPIC0: MPIO_C0 Pin, GPIO Input Data 0: Detect low level 1: Detect high level 116 Submit Documentation Feedback (Address: 7Eh, Read-Only RSV RSV GPIC3 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com GPIC2 GPIC1 GPIC0 N/A N/A N/A Copyright © 2010, Texas Instruments Incorporated ...

  • Page 117

    ... Orderable Device (1) Package Type Package Status PCM9211PT ACTIVE LQFP PCM9211PTR ACTIVE LQFP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 118

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing PCM9211PTR LQFP PT PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 1000 330.0 16.4 9.6 Pack Materials-Page 1 23-Jul-2010 Pin1 (mm) (mm) (mm) (mm) Quadrant 9.6 1.9 12.0 16 ...

  • Page 119

    ... Device Package Type PCM9211PTR LQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 1000 Pack Materials-Page 2 23-Jul-2010 Width (mm) Height (mm) 346.0 346.0 33.0 ...

  • Page 120

    PT (S-PQFP-G48) 0, 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 121

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...