IC AUDIO PWM PROC 64TQFP

TAS5508APAGR

Manufacturer Part NumberTAS5508APAGR
DescriptionIC AUDIO PWM PROC 64TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAGR datasheet
 


Specifications of TAS5508APAGR

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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TAS5508
8-Channel Digital Audio PWM Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES091D
February 2004 – Revised July 2009

TAS5508APAGR Summary of contents

  • Page 1

    TAS5508 8-Channel Digital Audio PWM Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ...

  • Page 2

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 ................................................................................................................ 1 Introduction PWM ....................................................................................................................... 1.1 Features ..................................................................................................................... 1.2 Overview 1.3 TAS5508 System Diagrams ........................................................................................................................ 2 Description 2.1 Physical Characteristics 2.1.1 Terminal Assignments 2.1.2 Ordering Information ...

  • Page 3

    Back-End Error (BKND_ERR) 3.2.4 Speaker/Headphone Selector (HP_SEL) 3.2.5 Mute (MUTE) 3.3 Device Configuration Controls 3.3.1 Channel Configuration Registers 3.3.2 Headphone Configuration Registers 3.3.3 Audio System Configurations 3.3.3.1 Using Line Outputs in 6-Channel Configurations 3.3.4 Recovery from Clock Error ...

  • Page 4

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2 6 Serial-Control I C Register Summary 7 Serial-Control Interface Register Definitions 7.1 Clock Control Register (0x00) 7.2 General Status Register 0 (0x01) 7.3 Error Status ...

  • Page 5

    TAS5508 Functional Structure 1-2 Typical TAS5508 Application (DVD Receiver) 1-3 Recommended TAS5508 and TAS5121 Channel Configuraton 2-1 TAS5508 DAP Architecture With I 2-2 TAS5508 Architecture With I 2-3 TAS5508 Detailed Channel Processing ........................................................................................................................ 2-4 5.23 Format 2-5 Conversion ...

  • Page 6

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 ....................................................................................................... 5-4 Single-Byte Read Transfer 5-5 Multiple-Byte Read Transfer 6 List of Figures ..................................................................................................... www.ti.com 67 68 Submit Documentation Feedback ...

  • Page 7

    ... Device Outputs During Power Down 3-4 Device Outputs During Back-End Error 3-5 Description of the Channel Configuration Registers (0x05 to 0x0C) 3-6 Recommended TAS5508 Configurations for Texas Instruments Power Stages 3-7 Audio System Configuration (General Control Register 0xE0) ...................................................................................................... 3-8 Volume Ramp Rates in ms ...

  • Page 8

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7-23 Channel-8 DRC2 Control Register Format 7-24 DRC1 Data Register Format 7-25 DRC2 Data Register Format 7-26 DRC Bypass Register Format 7-27 Output Mixer Register Format ...

  • Page 9

    ... Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PurePath Digital is a trademark of Texas Instruments. Matlab is a trademark of Math Works, Inc. All other trademarks are the property of their respective owners. ...

  • Page 10

    ... This enables the TAS5508 to provide an easy-to-use control interface with relaxed timing requirements. The TAS5508 can drive eight channels of H-bridge power stages. Texas Instruments H-bridge parts TAS5111, TAS5112, or TAS5182 with FETs are designed to work seamlessly with the TAS5508. The TAS5508 supports both single-ended or bridge-tied load configurations ...

  • Page 11

    AVSS AVDD DVSS DVDD VRD_PLL VRA_PLL VBGAP AVDD_REF AVSS_PLL AVDD_PLL VR_PLL Submit Documentation Feedback Output Control 8 2 Crossbar Mixer 8 8 Crossbar Mixer System Control Clock, PLL, and Serial Data I/F Figure 1-1. TAS5508 Functional Structure 8-Channel Digital ...

  • Page 12

    ... Figure 1-2. Typical TAS5508 Application (DVD Receiver) Figure 1-3 shows the recommended channel configuration when using the TAS5508 with the TAS5121 power stage. Note that each channel is normally dedicated to a particular function. 12 Introduction PWM AM Texas Instruments FM Digital Audio Amplifier Tuner TAS5508 MPEG Decoder Front-Panel Controls www ...

  • Page 13

    RIGHT BACK LEFT BACK SURROUND SURROUND + − + − TAS5121 TAS5121 Lineout Left PWM to Analog Lineout Right (Line Level) Figure 1-3. Recommended TAS5508 and TAS5121 Channel Configuraton Submit Documentation Feedback 8-Channel Digital Audio PWM Processor RIGHT SUBWOOFER ...

  • Page 14

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 14 Introduction PWM www.ti.com Submit Documentation Feedback ...

  • Page 15

    Description 2.1 Physical Characteristics 2.1.1 Terminal Assignments VRA_PLL PLL_FLT_RET PLL_FLTM PLL_FLTP AVSS AVSS VRD_PLL AVSS_PLL AVDD_PLL VBGAP RESET HP_SEL PDN MUTE DVDD DVSS 2.1.2 Ordering Information T A 0=C to 70=C Submit Documentation Feedback PAG PACKAGE (TOP VIEW) ...

  • Page 16

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2.1.3 Terminal Descriptions TERMINAL (1) TYPE TOLERANT NAME NO. AVDD_PLL 9 P AVSS AVSS_PLL 8 P BKND_ERR 37 DI DVDD 15 ...

  • Page 17

    TERMINAL (1) TYPE TOLERANT NAME NO. PWM_P_4 47 DO PWM_P_5 56 DO PWM_P_6 58 DO PWM_P_7 50 DO PWM_P_8 52 DO RESERVED 21, 22, 23, 64 RESET 11 DI SCL 25 DI SCLK 27 DI SDA 24 DIO SDIN1 ...

  • Page 18

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2.2 TAS5508 Functional Description Figure 2-1 shows the TAS5508 functional structure. The following sections describe the TAS5508 functional blocks: Power supply Clock, PLL, and serial data ...

  • Page 19

    Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508 accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I input using a 64-Fs SCLK clock ...

  • Page 20

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508 has separate audio-processing features ...

  • Page 21

    Table 2-2. TAS5508 Audio Processing Feature Sets 32 kHz–96 kHz FEATURE 8-CHANNEL FEATURE SET Signal-processing channels Pass-through channels Master volume 1 for 8 channels Individual channel volume controls Four bass and treble tone controls with =18-dB range, programmable corner ...

  • Page 22

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 (1) SDIN1-L ( Mixer 1 SDIN1-R (R) B SDIN2-L (LS 0x41) SDIN2-R (RS SDIN3-L (LBS) E Crossbar ...

  • Page 23

    SDIN1-L ( Mixer 1 SDIN1-R (R) B SDIN2-L (LS 0x41) SDIN2-R (RS SDIN3-L (LBS) E Crossbar SDIN3-R (RBS) F Input Mixer SDIN4-L (C) G SDIN4-R (LFE) H SDIN1-L (L) ...

  • Page 24

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 A_to_ipmix Left A SDIN1 B Right B_to_ipmix C_to_ipmix Left C SDIN2 D Right D_to_ipmix Biquads in Series E_to_ipmix Left Input Mixer E SDIN3 F Right F_to_ipmix ...

  • Page 25

    Bit −4 2 Bit −1 2 Bit 0 2 Bit 3 2 Bit Sign Bit The decimal value of a 5.23 format number can be found by following the weighting shown in the most significant bit is ...

  • Page 26

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I coefficient. The reason is that the 28-bit coefficient ...

  • Page 27

    Coefficient Coefficient Coefficient Digit 16 Digit 15 Digit 14 Integer Digit 4 8 (Bit 2 ) Integer Integer Digit 5 Digit ...

  • Page 28

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Ideal Input Maximum Signal Amplitude Signal Bits Input Figure 2-10. TAS5508 Digital Audio Processing 2.4 Input Crossbar Mixer The TAS5508 has a full 8=8 input crossbar ...

  • Page 29

    The five 28-bit coefficients for the each of the 56 biquads are programmable via the I Table 2-3. 48 – – All five coefficients for one biquad filter structure are written to one I 32-bit ...

  • Page 30

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 FS FILTER SET 1 FILTER SET 2 (kHz) BASS TREBLE BASS 32 42 917 1088 99 44.1 57 1263 115 48 63 1375 ...

  • Page 31

    This time interval is selectable via I 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default value is mask programmable. The input threshold value is ...

  • Page 32

    ... Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low-frequency attenuation near 60 Hz. The TAS5508 provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz, and EQ bandwidth = 60 Hz. Solution: Using Texas Instruments ALE TAS5508 DSP tool, Matlab™, or other signal-processing tool, develop a loudness function with the parameters listed in 32 ...

  • Page 33

    LOUDNESS DESCRIPTION TERM H(Z) Loudness biquad LG Loudness gain LO Loudness offset G Gain loudness ( OFF = 0) O Offset See Figure 2-15 for the resulting loudness function at different gains −10 −20 ...

  • Page 34

    ... If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It then outputs the TAS5508 hex coefficients for download to the TAS5508. ...

  • Page 35

    Region DRC Input Level Figure 2-17. Dynamic Range Compression (DRC) Transfer Function Structure The three regions shown in Thresholds T1 and T2 define region boundaries. Offsets O1 and O2 define the DRC gain coefficient settings ...

  • Page 36

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Slopes k0, k1, and k2 define whether compression or expansion performed within a given region, and the degree of compression or expansion to ...

  • Page 37

    Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. ...

  • Page 38

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2.10.2.3 Slope Parameter Computation In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within ...

  • Page 39

    Select Output N Select Output N Select Output N Select Output N Select Output N 2.12 PWM The TAS5508 has eight channels of high-performance digital PWM modulators that are designed to drive switching output stages (back ends) in both ...

  • Page 40

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 The PWM section also contains the power-supply volume control (PSVC) PWM. The interpolator, noise shaper, and PWM sections provide a PWM output with the following features: ...

  • Page 41

    ... Figure 2-21. Power-Supply and Digital Gains (Linear Space) 2.12.4 AM Interference Avoidance Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments' patented AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5508 adjusts the radiated emissions to provide an emission-clear zone for the tuned AM frequency ...

  • Page 42

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Analog Receiver Figure 2-22. Block Diagrams of Typical Systems Requiring TAS5508 Automatic AM 42 Description ADC Audio PCM1802 DSP Audio DSP Provides the Master and Bit ...

  • Page 43

    TAS5508 Controls and Status The TAS5508 provides control and status information from both the I This section describes some of these controls and status functions. The I register descriptions are contained Status Registers ...

  • Page 44

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the ...

  • Page 45

    CONTROL Bass filter sets Loudness (5508) AM interference enable AM interference IF AM interference select sequence Tuned frequency and mode Subwoofer PSVC control PSVC and PSVC range After the initialization time, the TAS5508 starts the transition to the operational ...

  • Page 46

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 3.2.3 Back-End Error (BKND_ERR) Back-end error is used to provide error management for back-end error conditions. Back-end error is a level-sensitive signal. Back-end error can be ...

  • Page 47

    The master mute terminal is used to support a variety of other operations in the TAS5508, such as setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command by the master ...

  • Page 48

    ... SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 3-6 lists the optimal setting for each output-stage configuration. Note that the default value is applicable in all configurations except the TAS5182 SE/BTL configuration. Table 3-6. Recommended TAS5508 Configurations for Texas Instruments Power Stages DEVICE ERROR RECOVERY RES ...

  • Page 49

    Table 3-7. Audio System Configuration (General Control Register 0xE0) Audio System 6 channels or 5.1 not using PSVC 6 channels using PSVC 5.1 system using PSVC 8 channels or 7.1 not using PSVC (default) 8 channels using PSVC 7.1 ...

  • Page 50

    ... This is also the default setting of the TAS5508. Default settings can be changed in the modulation index register (0x16). Note that no change should be made to this register when using Texas Instruments power stages. 3.3.8 Interchannel Delay An 8-bit value can be programmed into each of the eight PWM interchannel delay registers to add a delay per channel from 0 to 255 clock cycles ...

  • Page 51

    The TAS5508 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK. However, there is no constraint as to the phase relationship of these signals. The TAS5508 accepts a 64 = Fs SCLK rate and a ...

  • Page 52

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 3.5.1 Manual Bank Selection The three bank selection bits of the bank control register allow the appropriate bank to be manually selected (000 = bank 1, ...

  • Page 53

    Bank-Switching Example 1 Problem: The audio unit containing a TAS5508 needs to handle different audio formats with different sample rates. Format #1 requires kHz, format #2 requires Fs = 44.1 kHz, and format #3 requires ...

  • Page 54

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 54 TAS5508 Controls and Status www.ti.com Submit Documentation Feedback ...

  • Page 55

    Electrical Specifications 4.1 Absolute Maximum Ratings Supply voltage, DVDD and DVD_PWM Supply voltage, AVDD_PLL 3.3-V digital input Input voltage 5 V tolerant 1.8 V LVCMOS I Input clamp current (V < Output ...

  • Page 56

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 4.5 Electrical Characteristics Over recommended operating conditions (unless otherwise noted) PARAMETER V High-level output voltage OH V Low-level output voltage OL I High-impedance output current OZ ...

  • Page 57

    PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted) PARAMETER External VRA_PLL decoupling 4.7.2 Serial Audio Port Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER f SCLK input frequency ...

  • Page 58

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2 4.7 Serial Control Port Operation 2 Timing characteristics for I C interface signals over recommended operating conditions PARAMETER f Frequency, SCL SCL t ...

  • Page 59

    Reset Timing (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted) t Time to M-STATE low r(DMSTATE) t Pulse duration, RESET active w(RESET Time to enable I C r(I2C_ready) t Device start-up time r(run) ...

  • Page 60

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 4.7.6 Back-End Error (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER t Pulse duration, BKND_ERR active w(ER) t p(valid_low ...

  • Page 61

    Headphone Select (HP_SEL) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER t Pulse duration, HP_SEL active w(MUTE) t Soft volume update time d(VOL) t Switchover time (SW) (1) See the Volume Treble and Base Slew ...

  • Page 62

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 4.7.9 Volume Control Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER Maximum attenuation before mute Maximum gain Maximum volume before the onset of ...

  • Page 63

    Left-Justified Timing Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the ...

  • Page 64

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 4.8.3 Right-Justified Timing Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the ...

  • Page 65

    I C Serial-Control Interface (Slave Address 0x36) The TAS5508 has a bidirectional I supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not ...

  • Page 66

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 During multiple-byte write operations, the TAS5508 compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress ...

  • Page 67

    Incremental Multiple-Byte Write 2 The I C supports a special mode which permits I write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device ...

  • Page 68

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 5.7 Multiple-Byte Read A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data bytes are transmitted by the TAS5508 to the ...

  • Page 69

    Serial-Control I C Register Summary The TAS5508 slave address is 0x36. See Serial-Control Interface Register Definitions, complete bit definitions. Note that u indicates unused bits. 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS 0x00 1 Clock control ...

  • Page 70

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS Input mixer registers, 0x41–0x48 32/reg. Ch1–Ch8 0x49 4 ipmix_1_to_ch8 0x4A 4 ipmix_2_to_ch8 0x4B 4 ipmix_7_to_ch2 0x4C 4 Ch7_bp_bq2 ...

  • Page 71

    TOTAL I C REGISTER FIELDS BYTES SUBADDRESS Ch8 DRC2 slope k0 0x9F 12 Ch8 DRC2 slope k1 Ch8 DRC2 slope k2 Ch8 DRC2 offset 1 0xA0 16 Ch8 DRC2 offset 2 Ch8 DRC2 attack Ch8 DRC2 (1 – ...

  • Page 72

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS 0xD9 4 Master volume 0xDA 4 Bass filter set register 0xDB 4 Bass filter index register 0xDC 4 ...

  • Page 73

    Serial-Control Interface Register Definitions Unless otherwise noted, the I Note that u indicates unused bits. 7.1 Clock Control Register (0x00) Bit D1 is Don't Care – – ...

  • Page 74

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7.3 Error Status Register (0x02) Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must ...

  • Page 75

    Table 7-6. Channel Configuration Control Register Format – – – – 1 – – – – – 0 – – – – 1 – – – – – 0 – – – – ...

  • Page 76

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-8. Serial Data Interface Control Register Format (continued) RECEIVE SERIAL DATA INTERFACE FORMAT Left-justified Left-justified Left-justified Reserved Reserved Reserved ...

  • Page 77

    Automute Control Register (0x14) Table 7-10. Automute Control Register Format – – – – 0 – – – – 0 – – – – 0 – – – – 0 – – – ...

  • Page 78

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15) Table 7-11. Automute PWM Threshold and Back-End Reset Period Register Format ...

  • Page 79

    Modulation Index Limit Register (0x16) Bits D7–D3 are Don't Care. Table 7-12. Modulation Index Limit Register Format 7.13 Interchannel Delay Registers (0x1B–0x22) Channels and 8 are ...

  • Page 80

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-15. Bank-Switching Command Register Format D31 D30 D29 D28 D27 D26 D23 D22 D21 D20 D19 D18 – 0 – 0 – 0 – 0 ...

  • Page 81

    Table 7-16. Channel 1–8 Input Mixer Register Format TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[1] B_to_ipmix[1] C_to_ipmix[1] D_to_ipmix[1] 0x41 32 E_to_ipmix[1] F_to_ipmix[1] G_to_ipmix[1] H_to_ipmix[1] A_to_ipmix[2] B_to_ipmix[2] C_to_ipmix[2] D_to_ipmix[2] 0x42 32 E_to_ipmix[2] F_to_ipmix[2] G_to_ipmix[2] H_to_ipmix[2] A_to_ipmix[3] B_to_ipmix[3] C_to_ipmix[3] ...

  • Page 82

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-16. Channel 1–8 Input Mixer Register Format (continued TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[4] B_to_ipmix[4] C_to_ipmix[4] D_to_ipmix[4] 0x44 32 E_to_ipmix[4] F_to_ipmix[4] G_to_ipmix[4] ...

  • Page 83

    Table 7-16. Channel 1–8 Input Mixer Register Format (continued TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[7] B_to_ipmix[7] C_to_ipmix[7] D_to_ipmix[7] 0x47 32 E_to_ipmix[7] F_to_ipmix[7] G_to_ipmix[7] H_to_ipmix[7] A_to_ipmix[8] B_to_ipmix[8] C_to_ipmix[8] D_to_ipmix[8] 0x48 32 E_to_ipmix[8] F_to_ipmix[8] G_to_ipmix[8] H_to_ipmix[8] Submit Documentation ...

  • Page 84

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7.17 Bass Management Registers (0x49–0x50) Registers 0x49–0x50 provide configuration control for bass mangement. Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a ...

  • Page 85

    Table 7-19. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) (continued) DESCRIPTION b coefficient u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7: coefficient u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7: coefficient u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7: ...

  • Page 86

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-22. Channel 1–7 DCR1 Control Register Format (continued) D15 D14 D13 D12 D11 0 0 – – – – ...

  • Page 87

    DRC2 Control Register, Channel 8 (0x97) Table 7-23. Channel-8 DRC2 Control Register Format D31– Channel 8 (node r): no DRC Channel 8 (node r): pre-volume DRC 0 0 ...

  • Page 88

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 2 TOTAL I C REGISTER NAME BYTES SUBADDRESS Channel 8 DRC2 energy 0x9D 8 Channel 8 DRC2 (1 – energy) Channel 8 DRC2 threshold upper 16 ...

  • Page 89

    Table 7-27. Output Mixer Register Format (Upper 4 Bytes) (continued) D31 D30 D29 D28 D27 G27 D23 D22 D21 ...

  • Page 90

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-29. Output Mixer Register Format (Upper 4 Bytes) (continued) D31 D30 D29 D28 D27 G27 D23 D22 D21 D20 D19 G23 ...

  • Page 91

    Volume Biquad Register (0xCF) Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-32. ...

  • Page 92

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7.29 Volume, Treble, and Bass Slew Rates Register (0xD0) Table 7-33. Volume Gain Update Rate (Slew Rate) D31–D10 512-step update at ...

  • Page 93

    VOLUME INDEX (H) 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 044 045 046 047 048 049 04A 04B 04C 240 241 242 243 244 245 3FF Submit Documentation Feedback Table ...

  • Page 94

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 7.31 Bass Filter Set Register (0xDA) Bits D31-D27, D23-D19, D15-D11, and D7-D3 are Don't Care. D31 D30 D29 D28 D27 ...

  • Page 95

    Table 7-40. Channels 7, 2, and 1 (Center, Right Front, and Left Front ...

  • Page 96

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 D31 D30 D29 D28 D27 ...

  • Page 97

    Treble Filter Index (0xDD) Index values above 0x24 are invalid. Table 7-47. Treble Filter Index Register Format TOTAL BYTES SUBADDRESS 0xDD 4 Treble filter index (TFI) TREBLE INDEX VALUE 0x00 0x01 0x02 0x03 0x04 0x05 ...

  • Page 98

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 Table 7-50. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE) D15 D14 D13 D12 D11 – – – ...

  • Page 99

    PSVC Range Register (0xDF) Bits D31–D2 are zero. D31– 12.04-dB control range for PSVC 18.06-dB control range for PSVC 24.08-dB control range for PSVC ...

  • Page 100

    TAS5508 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 100 Serial-Control Interface Register Definitions www.ti.com Submit Documentation Feedback ...

  • Page 101

    TAS5508 Example Application Schematic The following page contains an example application schematic for the TAS5508. Submit Documentation Feedback 8-Channel Digital Audio PWM Processor SLES091D – FEBRUARY 2004 – REVISED JULY 2009 TAS5508 Example Application Schematic TAS5508 101 ...

  • Page 102

    Phono socket J950 LINE OUTPUT Phono socket J951 GND +5.0V J900 4 3 HEADPHONE OUTPUT 2 1 Mini-Jack (3.5mm) C C10 R10 R11 C13 10nF 200R ...

  • Page 103

    PACKAGING INFORMATION (1) Orderable Device Status TAS5508PAG NRND TAS5508PAGG4 NRND TAS5508PAGR NRND TAS5508PAGRG4 NRND (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be ...

  • Page 104

    PAG (S-PQFP-G64) 0, 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 105

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...