IC DIGITAL AUDIO PWM 8CH 64-TQFP

TAS5508BPAGR

Manufacturer Part NumberTAS5508BPAGR
DescriptionIC DIGITAL AUDIO PWM 8CH 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508BPAGR datasheet
 


Specifications of TAS5508BPAGR

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-26679-2
TAS5508BPAGR
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TAS5508B
8-Channel Digital Audio PWM Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES162C
December 2005 – Revised July 2009

TAS5508BPAGR Summary of contents

  • Page 1

    TAS5508B 8-Channel Digital Audio PWM Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ...

  • Page 2

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 ......................................................................................................................... 1 Introduction ....................................................................................................................... 1.1 Features ..................................................................................................................... 1.2 Overview 1.3 Changes From the TAS5508A to the TAS5508B 1.4 TAS5508B System Diagrams ........................................................................................................................ 2 Description 2.1 Physical ...

  • Page 3

    Power Down (PDN) 3.2.3 Back-End Error (BKND_ERR) 3.2.3.1 BKND_ERR and VALID 3.2.4 Speaker/Headphone Selector (HP_SEL) 3.2.5 Mute (MUTE) 3.3 Device Configuration Controls 3.3.1 Channel Configuration Registers 3.3.2 Headphone Configuration Registers 3.3.3 Audio System Configurations 3.3.3.1 Using Line Outputs ...

  • Page 4

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 ......................................................................................................... 5.4 Multiple-Byte Write 5.5 Incremental Multiple-Byte Write ........................................................................................................... 5.6 Single-Byte Read ......................................................................................................... 5.7 Multiple-Byte Read 2 6 Serial-Control I C Register Summary 7 Serial-Control Interface ...

  • Page 5

    TAS5508B Functional Structure 1-2 Typical TAS5508B Application (DVD Receiver) 1-3 Pass-Through Output Mixer TAS5508B Channel Configuration 2-1 TAS5508B DAP Architecture With I 2-2 TAS5508B Architecture With I 2-3 TAS5508B Detailed Channel Processing ........................................................................................................................ 2-4 5.23 Format 2-5 Conversion ...

  • Page 6

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 5-3 Multiple-Byte Write Transfer ....................................................................................................... 5-4 Single-Byte Read Transfer 5-5 Multiple-Byte Read Transfer 6 List of Figures ..................................................................................................... ..................................................................................................... www.ti.com Submit Documentation Feedback ...

  • Page 7

    ... Device Outputs During Power Down 3-4 Device Outputs During Back-End Error 3-5 Description of the Channel Configuration Registers (0x05 to 0x0C) 3-6 Recommended TAS5508B Configurations for Texas Instruments Power Stages 3-7 Audio System Configuration (General Control Register 0xE0) 3-8 Volume Ramp Periods in ms 7-1 ...

  • Page 8

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7-23 DRC Bypass Register Format 7-24 Output Mixer Register Format (Upper 4 Bytes) 7-25 Output Mixer Register Format (Lower 4 Bytes) 7-26 Output Mixer Register Format ...

  • Page 9

    ... Digital De-Emphasis for 32-, 44.1-, and 48-kHz Data Rates – Flexible Automute Logic With Programmable Threshold and Duration for Noise-Free Operation – Intelligent AM Interference-Avoidance System Provides Clear AM Reception – Power-Supply Volume Control (PSVC) Copyright © 2005–2009, Texas Instruments Incorporated TAS5508B ...

  • Page 10

    ... This enables the TAS5508B to provide an easy-to-use control interface with relaxed timing requirements. The TAS5508B can drive eight channels of H-bridge power stages. Texas Instruments power stage parts TAS5111, TAS5112, or TAS5182 with FETs are designed to work seamlessly with the TAS5508B. The TAS5508B supports either the single-ended or bridge-tied-load configuration ...

  • Page 11

    AVSS AVDD DVSS DVDD VRD_PLL VRA_PLL VBGAP AVDD_REF AVSS_PLL AVDD_PLL VR_PLL Submit Documentation Feedback Output Control 8 2 Crossbar Mixer 8 8 Crossbar Mixer Clock, PLL, and Serial Data I/F Figure 1-1. TAS5508B Functional Structure 8-Channel Digital Audio PWM ...

  • Page 12

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 1.3 Changes From the TAS5508A to the TAS5508B High-pass filter is enabled by default (0x03 bit register 0xD0 bit 30 is added ...

  • Page 13

    ... TAS5121 TAS5121 Lineout Left PWM to Analog Lineout Right (Line Level) Figure 1-3. Pass-Through Output Mixer TAS5508B Channel Configuration Submit Documentation Feedback 8-Channel Digital Audio PWM Processor AM Texas Instruments FM Digital Audio Amplifier Tuner MPEG Decoder Front-Panel Controls RIGHT SUBWOOFER CENTER SURROUND + − ...

  • Page 14

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 2 Description 2.1 Physical Characteristics 2.1.1 Terminal Assignments VRA_PLL PLL_FLT_RET PLL_FLTM PLL_FLTP AVSS AVSS VRD_PLL AVSS_PLL AVDD_PLL VBGAP RESET HP_SEL PDN MUTE DVDD DVSS 2.1.2 Ordering ...

  • Page 15

    Terminal Descriptions TERMINAL (1) TYPE TOLERANT NAME NO. AVDD_PLL 9 P AVSS AVSS_PLL 8 P BKND_ERR 37 DI DVDD 15 DVDD_PWM 54 P DVSS 16, 34, P 35, 38 DVSS_PWM 53 P HP_SEL ...

  • Page 16

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 TERMINAL (1) TYPE TOLERANT NAME NO. PWM_P_4 47 DO PWM_P_5 56 DO PWM_P_6 58 DO PWM_P_7 50 DO PWM_P_8 52 DO RESERVED 21, 22, 23, 64 ...

  • Page 17

    TAS5508B Functional Description Figure 1-1 shows the TAS5508B functional structure. The following sections describe the TAS5508B functional blocks: Power supply Clock, PLL, and serial data interface serial-control interface Device control Digital audio processor (DAP) 2.2.1 ...

  • Page 18

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508B accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, ...

  • Page 19

    To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508B has separate audio-processing features for 32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz. ...

  • Page 20

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Table 2-2. TAS5508B Audio-Processing Feature Sets 32 kHz–96 kHz FEATURE 8-CHANNEL FEATURE SET Signal-processing channels Pass-through channels Master volume 1 for 8 channels Individual channel volume ...

  • Page 21

    SDIN1-L ( Mixer 1 SDIN1-R (R) B SDIN2-L (LS 0x41) SDIN2-R (RS SDIN3-L (LBS) E Crossbar SDIN3-R (RBS) F Input Mixer SDIN4-L (C) G SDIN4-R (LFE) H SDIN1-L (L) ...

  • Page 22

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 (1) SDIN1-L ( Mixer 1 SDIN1-R (R) B SDIN2-L (LS 0x41) SDIN2-R (RS SDIN3-L (LBS) E Crossbar ...

  • Page 23

    A_to_ipmix Left A SDIN1 B Right B_to_ipmix C_to_ipmix Left C SDIN2 D Right D_to_ipmix Biquads in Series E_to_ipmix Left Input Mixer E SDIN3 F Right F_to_ipmix G_to_ipmix Left G SDIN4 H Right H_to_ipmix Figure 2-3. TAS5508B Detailed Channel Processing ...

  • Page 24

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 −23 2 Bit −4 2 Bit −1 2 Bit 0 2 Bit 3 2 Bit Sign Bit The decimal value of a 5.23 format number can ...

  • Page 25

    I coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient ...

  • Page 26

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Coefficient Coefficient Coefficient Digit 16 Digit 15 Digit 14 Integer Digit 4 8 (Bit 2 ...

  • Page 27

    Ideal Input Maximum Signal Amplitude Signal Bits Input Figure 2-10. TAS5508B Digital Audio Processing 2.4 Input Crossbar Mixer The TAS5508B has a full 8 8 input crossbar mixer. This mixer permits each signal-processing channel input to be any mix ...

  • Page 28

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a ...

  • Page 29

    L and R Sub The bass and treble filters use a soft update rate that does not produce artifacts during adjustment FILTER SET 1 FILTER SET 2 (kHz) BASS TREBLE BASS 32 42 917 ...

  • Page 30

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 2.8 Automute and Mute Channel Controls The TAS5508B has individual channel automute controls that are enabled via I and D6 (the default setting is enabled). Two ...

  • Page 31

    TAS5508B loudness implementation tracks the volume control setting to provide spectral compensation for weak low- or high-frequency response at low volume levels. For the volume tracking function, both linear and logarithmic control laws can be implemented. Any biquad filter ...

  • Page 32

    ... TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Solution: Using Texas Instruments ALE TAS5508B DSP tool, Matlab™, or other signal-processing tool, develop a loudness function with the parameters listed in Table 2-7. Example Loudness Function Parameters LOUDNESS ...

  • Page 33

    ... If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It then outputs the TAS5508B hex coefficients for download to the TAS5508B. ...

  • Page 34

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Figure 2-17 illustrates a typical DRC transfer function. Region DRC Input Level Figure 2-17. Dynamic Range Compression (DRC) Transfer Function Structure The ...

  • Page 35

    Slopes k0, k1, and k2 define whether compression or expansion performed within a given region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format) numbers. 2.10.1 DRC Implementation ...

  • Page 36

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB) or cut (< 0 dB) ...

  • Page 37

    Slope Parameter Computation In developing the equations used to determine the subaddress of the input value required to realize a given compression or expansion within a given region of the DRC, the following convention is adopted. DRC transfer ...

  • Page 38

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Select Output N Select Output N Select Output N Select Output N Select Output N 2.12 PWM The TAS5508B has eight channels of high-performance digital PWM ...

  • Page 39

    The PWM section also contains the power-supply volume control (PSVC) PWM. The interpolator, noise shaper, and PWM sections provide a PWM output with the following features oversampling – 44.1 kHz, 48 kHz, ...

  • Page 40

    ... Figure 2-21. Power-Supply and Digital Gains (Log Space) 2.12.4 AM Interference Avoidance Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments' patented AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5508B adjusts the radiated emissions to provide an emission-clear zone for the tuned AM frequency ...

  • Page 41

    Analog Receiver Figure 2-22. Block Diagrams of Typical Systems Requiring TAS5508B Automatic AM Submit Documentation Feedback 8-Channel Digital Audio PWM Processor ADC Audio PCM1802 DSP Audio DSP Provides the Master and Bit Clocks Digital Audio Receiver DSP The Digital ...

  • Page 42

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 3 TAS5508B Controls and Status The TAS5508B provides control and status information from both the I This section describes some of these controls and status functions. ...

  • Page 43

    Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard-mute state (M-state) to the operational state is performed using a quiet start-up ...

  • Page 44

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 After the initialization time, the TAS5508B starts the transition to the operational state with the master volume set at mute. Because the TAS5508B has an external ...

  • Page 45

    BKND_ERR and VALID The number of channels that are affected by the BKND_ERR signal depends on the setting of bit register 0xE0. If the I C setting is 0 (8-channel mode), the ...

  • Page 46

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 3.3 Device Configuration Controls The TAS5508B provides a number of system configuration controls that are set at initialization and following a reset. Channel configuration Headphone configuration ...

  • Page 47

    ... Table 3-6. Recommended TAS5508B Configurations for Texas Instruments Power Stages DEVICE ERROR RECOVERY RES TAS5111 (default) AUT RES TAS5112 AUT TAS5182 RES RES: To recover from a shutdown, the output stage requires VALID to go low. AUT: The power stage can auto-recover from a shutdown. ...

  • Page 48

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 3.3.3.1 Using Line Outputs in 6-Channel Configurations The audio system can be configured for a 6-channel configuration (with 2 lineouts) by writing bit ...

  • Page 49

    TAS5508B output needs to get ready for the next on-time period. The maximum possible modulation is then set by the power stage requirements. The default modulation index limit setting is 97.7%; however, some power stages may ...

  • Page 50

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Five bass filter-set selections (register 0xDA) Five treble filter-set selections (register 0xDC) The default selection for bank control is manual bank with bank 1 selected. Note ...

  • Page 51

    Bank-Switch Timeline After a bank switch is initiated (manual or automatic minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate. 3.5.5 Bank-Switching Example 1 Problem: The ...

  • Page 52

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 4 Electrical Specifications 4.1 Absolute Maximum Ratings Supply voltage, DVDD and DVD_PWM Supply voltage, AVDD_PLL 3.3-V digital input Input voltage 5-V tolerant 1.8-V LVCMOS I Input ...

  • Page 53

    Electrical Characteristics Over recommended operating conditions (unless otherwise noted) PARAMETER V High-level output voltage OH V Low-level output voltage OL I High-impedance output current OZ I Low-level input current IL I High-level input current IH I Input supply ...

  • Page 54

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 4.7.2 Serial Audio Port Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER f SCLK input frequency SCLKIN t Setup time, LRCLK ...

  • Page 55

    TAS5508B Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode 2 I C-Bus Devices All values are referred to V and V IHmin A PARAMETER f SCL clock frequency SCL Hold time (repeated) START condition. t ...

  • Page 56

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 2 4.7.4.1 Recommended I C Pullup Resistors recommended that the I C pullup resistors R (see Figure 4-4), then the series resistor R ...

  • Page 57

    Reset Timing (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted) t Time from reset to PWM_EN low (PWM outputs disabled) d(PWM_off) t Pulse duration, RESET active w(RESET Time to enable I C d(I2C_ready) ...

  • Page 58

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 4.7.7 Back-End Error (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER t Pulse duration, BKND_ERR active w(ER) t Time from back-end error ...

  • Page 59

    Headphone Select (HP_SEL) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER t Pulse duration, HP_SEL active w(HP_SEL) t Soft volume update time d(VOL) t Switchover time (SW) (1) See the Volume, Treble, and Base Slew ...

  • Page 60

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 4.8 Serial Audio Interface Control and Timing 2 4.8 Timing timing uses LRCLK to define when the data being transmitted is ...

  • Page 61

    Left-Justified Timing Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the ...

  • Page 62

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 4.8.3 Right-Justified Timing Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the ...

  • Page 63

    I C Serial-Control Interface (Slave Addresses 0x36 and 0x37) The TAS5508B has a bidirectional I supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that ...

  • Page 64

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 5.2 Single- and Multiple-Byte Transfers The serial-control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the ...

  • Page 65

    Multiple-Byte Write A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data bytes are transmitted by the master device to TAS5508B, as shown in data byte, the TAS5508B responds with an acknowledge bit. ...

  • Page 66

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 5.6 Single-Byte Read As shown in Figure 5-4, a single-byte, data-read transfer begins with the master device transmitting a start 2 condition followed by the I ...

  • Page 67

    Serial-Control I C Register Summary The TAS5508B slave write address is 0x36 and the read address is 0x37. See Serial-Control Interface Register Definitions, Section 7 Note that u indicates unused bits. 2 TOTAL I C REGISTER FIELDS ...

  • Page 68

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS 0x4F 4 Ch8_bp_bq2 0x50 4 Ch8_bq2 0x51–0x88 20/reg. Biquad filter register 0x89–0x90 8 Bass and treble bypass register, ...

  • Page 69

    TOTAL I C REGISTER FIELDS BYTES SUBADDRESS DRC bypass 1 0xA2 8 DRC inline 1 DRC bypass 2 0xA3 8 DRC inline 2 DRC bypass 3 0xA4 8 DRC inline 3 DRC bypass 4 0xA5 8 DRC inline ...

  • Page 70

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS 0xE1–0xFD 0xFE 4 (min) Multiple-byte write-append register 0xFF 2 70 Serial-Control I C Register Summary DESCRIPTION OF CONTENTS ...

  • Page 71

    Serial-Control Interface Register Definitions Unless otherwise noted, the I Note that u indicates unused bits. 7.1 Clock Control Register (0x00) Bit D1 is don't care – – ...

  • Page 72

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.4 System Control Register 2 (0x04) Bits D3 and D2 are don't care. Table 7-4. System Control Register-2 Format – ...

  • Page 73

    Headphone Configuration Control Register (0x0D) Bit D0 is don't care. Table 7-6. Headphone Configuration Control Register Format – – – – 1 – – – – – 0 – – – – ...

  • Page 74

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.8 Soft Mute Register (0x0F) Do not use this register if using the remapped output mixer configuration – – – – – – ...

  • Page 75

    Automute Control Register (0x14) For more information on how to use this register, see Automute and Mute Channel Controls, Table 7-9. Automute Control Register Format – – – – 0 – – – ...

  • Page 76

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.10 Output Automute PWM Threshold and Back-End Reset Period Register (0x15) For more information on how to use this register, see Automute and Mute Channel Controls, ...

  • Page 77

    ... Modulation Index Limit Register (0x16) Bits D7–D3 are don't care. Note that some power stages require a lower modulation limit than the default of 97.7%. Contact Texas Instruments for more details about the requirements for a particular power stage. Table 7-11. Modulation Index Limit Register Format ...

  • Page 78

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.12 Bank-Switching Command Register (0x40) Bits D31–D24, D22–D19 are don't care. Table 7-12. Bank-Switching Command Register Format D31 D30 D29 D28 D27 D26 D23 D22 D21 ...

  • Page 79

    Input Mixer Registers, Channels 1–8 (0x41–0x48) Input mixers and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48, respectively. Each gain coefficient is in 28-bit (5.23) ...

  • Page 80

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Table 7-13. Channel 1–8 Input Mixer Register Format (continued TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[3] B_to_ipmix[3] C_to_ipmix[3] D_to_ipmix[3] 0x43 32 E_to_ipmix[3] F_to_ipmix[3] G_to_ipmix[3] ...

  • Page 81

    Table 7-13. Channel 1–8 Input Mixer Register Format (continued TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[6] B_to_ipmix[6] C_to_ipmix[6] D_to_ipmix[6] 0x46 32 E_to_ipmix[6] F_to_ipmix[6] G_to_ipmix[6] H_to_ipmix[6] A_to_ipmix[7] B_to_ipmix[7] C_to_ipmix[7] D_to_ipmix[7] 0x47 32 E_to_ipmix[7] F_to_ipmix[7] G_to_ipmix[7] H_to_ipmix[7] A_to_ipmix[8] B_to_ipmix[8] ...

  • Page 82

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.14 Bass Management Registers (0x49–0x50) Registers 0x49–0x50 provide configuration control for bass mangement. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a ...

  • Page 83

    Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 7-16. Contents of One 20-Byte Biquad ...

  • Page 84

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.18 DRC1 Control Registers, Channels 1–7 (0x96) Bits D31–D14 are don't care. Note that there must be a 10-ms delay between a write to register 0x96 ...

  • Page 85

    DRC2 Control Register, Channel 8 (0x97) Note that there must be a 10-ms delay between a write to register 0x96 and a write to register 0x97. Table 7-20. Channel-8 DRC2 Control Register Format D31– ...

  • Page 86

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.21 DRC2 Data Registers (0x9D–0xA1) DRC2 applies to channel 8. 2 TOTAL I C REGISTER NAME BYTES SUBADDRESS Channel 8 DRC2 energy 0x9D 8 Channel 8 ...

  • Page 87

    DAP channel 6 is mapped though the 8 2 crossbar mixer (0xAF) to PWM channel 6 Note that the pass-through output mixer configuration (0xD0 bit recommended. Using the remapped output mixer configuration (0xD0 bit 30 ...

  • Page 88

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 Note that the default setting is recommended for most systems. Any variation from this setting increases the complexity of using some features such as volume and ...

  • Page 89

    Table 7-28. Output Mixer Register Format (Lower 4 Bytes) (continued) D31 D30 D29 D28 D27 G27 D23 D22 D21 D20 D19 G23 G22 ...

  • Page 90

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.26 Volume, Treble, and Bass Slew Rates Register (0xD0) If using pass-through output mixer configuration, bit D30 must to be set to 1 after reset. For ...

  • Page 91

    VOLUME INDEX (H) Submit Documentation Feedback Table 7-33. Master and Individual Volume Controls 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 TO 044 045 046 047 048 049 04A 04B 04C ...

  • Page 92

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.28 Bass Filter Set Register (0xDA) To use the bass and treble function, the bass and treble bypass registers (0x89–0x90) must be configured as inline (default ...

  • Page 93

    Table 7-37. Channels 7, 2, and 1 (Center, Right Front, and Left Front ...

  • Page 94

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 7.30 Treble Filter Set Register (0xDC) Bits D31–D27 are don't care. To use the bass and treble function, the bass and treble bypass registers (0x89 - ...

  • Page 95

    Bits D7–D3 are don't care. Table 7-43. Channels 7, 2, and 1 (Center, Right Front, and Left Front ...

  • Page 96

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 D31 D30 D29 D28 D27 D23 D22 D21 D20 D19 0 – 1 – – 0 – 0 – 1 – 1 – – – – ...

  • Page 97

    PSVC Range Register (0xDF) Bits D31–D2 are zero. D31– 12.04-dB control range for PSVC 18.06-dB control range for PSVC 24.08-dB control range for PSVC ...

  • Page 98

    TAS5508B 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 98 Serial-Control Interface Register Definitions www.ti.com Submit Documentation Feedback ...

  • Page 99

    TAS5508B Example Application Schematic The following page contains an example application schematic for the TAS5508B. Submit Documentation Feedback 8-Channel Digital Audio PWM Processor SLES162C – DECEMBER 2005 – REVISED JULY 2009 TAS5508B Example Application Schematic TAS5508B 99 ...

  • Page 100

    Phono socket J950 LINE OUTPUT Phono socket J951 GND +5.0V J900 4 3 HEADPHONE OUTPUT 2 1 Mini-Jack (3.5mm) C C10 R10 R11 C13 10nF 200R ...

  • Page 101

    ... TAS5508BPAG ACTIVE TAS5508BPAGG4 ACTIVE TAS5508BPAGR ACTIVE TAS5508BPAGRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 102

    PAG (S-PQFP-G64) 0, 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 103

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...