IC DGTL AUDIO PROCESSOR 100HTQFP

 

TAS3218PZPR

Manufacturer Part NumberTAS3218PZPR
DescriptionIC DGTL AUDIO PROCESSOR 100HTQFP
ManufacturerTexas Instruments
TypeAudio Processor
TAS3218PZPR datasheets

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Specifications of TAS3218PZPR

ApplicationsAudio routing, processingMounting TypeSurface Mount
Package / Case100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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.......................................................................................................................................................................................................
DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
FEATURES
1
Audio Input/Output
2
– 3 Synchronous Serial Audio Inputs
(6 Channels)
– 2 Synchronous Serial Audio Outputs
(4 Channels)
– Input and Output Data Formats: 16-, 20-, or
24-Bit Data Left, Right ,and I
– SPDIF Transmitter
– 64 Fs Bit Clock Rate
– 512 Fs XTAL Input for Master Mode Clock
Rates
– 256 Fs MCLKIN for Slave Mode Clock Rates
– 10 Multiplexed Stereo Analog Inputs
Selectable into 1 Stereo ADC and 3 Stereo
Line Outputs
– High Quality DNR: 93 dB (Typical) ADC
Channel Performance (2 Channels)
– 3 Single-Ended Analog Stereo Line Driver
Outputs With 1 of 11 Selectable Input, 10 k
– 100-pF Drive Capability (Typical Output
Level: 1 Vrms)
– 3 Stereo Audio DACs
– High-Quality DNR: 97 dB (Typical) DAC
Channel Performance (6 Channels)
– Stereo Headphone Amplifier 24 mW Power
Output into 16 , 100 pF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Audio Digital Signal Processor
– Programmable Functionality
– 135-MHz Operation
– 48-Bit Data Path With 76-Bit Accumulator
– Two Memory Loads and One Memory Store
Per Cycle
– Usable 768 Data RAM Words (48-Bit),
2
S
Usable 1K Coefficient RAM (28-Bit)
– Usable 2.5K Program RAM
– 360 ms at 48 kHz, 17408 Words 24-Bit Delay
Memory for Video Sync
System Control Processor
– Embedded 8051 WARP Microprocessor
– Programmable Using Standard 8051 C
Compilers
– 16K Words of Program RAM (8-Bit)
– 2048 Words of Data RAM (8-Bit)
– 256 Words of Internal RAM (8-Bit)
– Programmable Functionality
General Features
– Easy-to-Use Control Interface
2
– I
C Serial Control Master and Slave
Interface
– Control Interface Operational Without
External MCLK Input
– Single 3.3-V Power Supply
– Integrated Regulators
– 100-Pin TQFP (PZP) Package
TAS3218
SLES235 – JULY 2008
Copyright © 2008, Texas Instruments Incorporated

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TAS3218PZPR Summary of contents

  • Page 1

    ... Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty ...

  • Page 2

    ... For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Submit Documentation Feedback PZP PACKAGE (TOP VIEW) ORDERING INFORMATION (1) (2) ORDERABLE PART NUMBER TAS3218IPZP TAS3218IPZPR Tape and reel TAS3218PZP TAS3218PZPR Product Folder Link(s): TAS3218 www.ti.com 75 V1P5_REF 74 BG_REF 73 BIAS_REF 72 AVSS_ADC/REF 71 ...

  • Page 3

    ... Devices that drive inputs with pullups must be able to sink 20 A while maintaining a logic 0 drive level. Devices that drive inputs with pull-downs must be able to source 20 A while maintaining a logic 1 drive level. Copyright © 2008, Texas Instruments Incorporated TERMINAL FUNCTIONS (1) ...

  • Page 4

    ... Right-channel digital-to-analog converter output 1 Left-channel digital-to-analog converter output 2 Right-channel digital-to-analog converter output 2 Analog ground 3.3-V analog power 3.3-V analog power Left-channel headphone output Analog ground Right-channel headphone output 3.3-V analog power Product Folder Link(s): TAS3218 www.ti.com Copyright © 2008, Texas Instruments Incorporated ...

  • Page 5

    ... M8051 WARP controller, serial control interface, and device control Audio DSP digital audio processing Power supply Internal references Figure 1 shows the functional structure of the TAS3218. Copyright © 2008, Texas Instruments Incorporated TERMINAL FUNCTIONS (continued) (1) TERMINATION DESCRIPTION Analog ground External crystal input External crystal output Pin out of internal regulator ...

  • Page 6

    ... Ohm HP OUT 220 ohm 2 DACOUT 2L DACOUT A-MUX 2 LINEOUT 1L/R Apply to all Line and 11:1 DAC outputs A-MUX 2 LINEOUT 2L/R 10:1 10K ohm A-MUX 2 LINEOUT 3L/R 10:1 Line outputs DAC outputs Copyright © 2008, Texas Instruments Incorporated 1V RMS ( MAX ) 0.9 V RMS( MAX ) ...

  • Page 7

    ... MCLKB Clocks The TAS3218 can be configured as either the clock master or clock slave depending on the settings in the clock configuration register. By default, the TAS3218 is configured as the clock master. diagram of the TAS3218 clocks Copyright © 2008, Texas Instruments Incorporated OSC MCLKIN Clock SCLKIN Control ...

  • Page 8

    ... Clock ( spdif_tx_out SPDIF Transmitter (Audio Output Select - Control Bits [1:0] from SPDIF Control Register : 0x16) OUTMUX [1:0] SPDIF_MUTE (Mute Control Register : 0x09) 01 MCLKOUT 00 0 SPDIF_OUT/ 1* SDOUT2 1 0 SCLKOUT SPDIF _IN SDOUT 1 SAP OUT sdout2 LRCLKOUT Copyright © 2008, Texas Instruments Incorporated ...

  • Page 9

    ... Degradation in analog performance expected depending on the quality of MCLKIN. The TAS3218 device does not include any internal clock error or click/pop detection/management. The muting of the outputs at updating of sample rate dependent coefficients must be initiated by the host system controller. Copyright © 2008, Texas Instruments Incorporated ...

  • Page 10

    ... S format. The serial data input format is configurable via the NOTE commands to reconfigure the serial audio port (SAP) LSB MSB Figure 5. SAP I S Format 64 Fs Format Product Folder Link(s): TAS3218 32 clks Right Channel Copyright © 2008, Texas Instruments Incorporated www.ti.com LSB ...

  • Page 11

    ... All data are presented in 2's complement form with MSB first. Figure 7. SAP Right-Justified 64 Fs Format SAP Input and Output Normalization The TAS3218 supports SAP input and SAP output normalization. This supports simultaneous output to 2 left-justified and I S devices. Copyright © 2008, Texas Instruments Incorporated LSB MSB ...

  • Page 12

    ... I S, Left, or Right Justified MCLKIN SCLKIN External LRCLKIN Data Source SDIN Figure 8. SAP Output Normal Configuration (No Normalization) 12 Submit Documentation Feedback NOTE Left, or Right Justified MCLKOUT SCLKOUT TAS3208 LRCLKOUT SDOUT Product Folder Link(s): TAS3218 www.ti.com DAC Copyright © 2008, Texas Instruments Incorporated ...

  • Page 13

    ... External Data Source LRCLK SCLK SDIN Left-Justified LRCLK Left-Justified SDOUT Figure 9. SAP Output Configuration (I Copyright © 2008, Texas Instruments Incorporated TAS3218 LRCLK MSB MSB Left Channel Right Channel MSB MSB Right Channel Left Channel Left Normalization ON) Product Folder Link(s): TAS3218 TAS3218 SLES235 – ...

  • Page 14

    ... Left-Justified MSB SDIN Left Channel LRCLK SDOUT Figure 10. SAP Output Configuration (I 14 Submit Documentation Feedback MSB Right Channel MSB MSB Right Channel Left Channel Left Normalization OFF) Product Folder Link(s): TAS3218 www.ti.com MSB Left Channel Copyright © 2008, Texas Instruments Incorporated ...

  • Page 15

    ... SCLK Left Justified MSB SDIN Left Channel I2S LRCLK I2S SDOUT MSB Left Channel Figure 11. SAP Output Configuration (Left to I Copyright © 2008, Texas Instruments Incorporated TAS3208 Left Justified LRCLK MSB Right Channel MSB Right Channel 2 S Normalization ON) Product Folder Link(s): ...

  • Page 16

    ... Left Channel Right Channel 2 S Normalization OFF) Figure Serial Audio Port Transmitter SPDIF Encoder DAP Control Signals SPDIF Control Register Product Folder Link(s): TAS3218 www.ti.com 13. SDOUT2 Channel Mute Control SDOUT2/ SPDIF “0” Output Selector Copyright © 2008, Texas Instruments Incorporated ...

  • Page 17

    ... M8051 SFR register map for the S/PDIF module control. ADDR 7 xx00 RST xx01 CATEGORY xx10 SR xx11 The relationship of the M8051 SFR register map with I Copyright © 2008, Texas Instruments Incorporated Start of Channel Status Block Frame 0 Z Channel A Y Channel B One Sub-Frame 7 8 Audio Data Channel Status Data Figure 14 ...

  • Page 18

    ... Other control bits are mapped to subaddress 0x16. 18 Submit Documentation Feedback 2 C register mapping for controlling the SPDIF module. The mute control Product Folder Link(s): TAS3218 www.ti.com 2 C Registers Copyright © 2008, Texas Instruments Incorporated ...

  • Page 19

    ... EMP CLKAC WORDLEN RST ESFR Figure 15. I Specification Coverage The TAS3218 is covered by the following specificaiotns: IEC60956-1: Second Edition, 2004-03 IEC60956-3: Second Edition, 2003-01 IEC958-2: First Edition, 1994-07 Specifcation coverage details can be found in Copyright © 2008, Texas Instruments Incorporated AMUXes SDOUT2 SDOUT1 Decode 8 7 ...

  • Page 20

    ... H/W auto set (1 for left, 2 for right channel) Register settable (32,44.1,48 kHz only) Register settable H/W auto set according to register setting 24-bit original output sample is truncated to the specified word length. Fixed to all zero (not indicated) Copyright © 2008, Texas Instruments Incorporated ...

  • Page 21

    ... To avoid audio aritifacts when using the line driver outputs, I reconfigure the lineout multiplexers should not be issued alone, rather should be accompanied by a mute/unmute sequence to all analog audio channels of the TAS3218. Copyright © 2008, Texas Instruments Incorporated NOTE: Product Folder Link(s): TAS3218 TAS3218 SLES235 – ...

  • Page 22

    ... Force MUTE OFF 1 0 Force MUTE ON Figure 16. Analog Input/Output Product Folder Link(s): TAS3218 ADC + DAC 1 – V REF DAC 2 DAC 3 BIT MUTE Block 7 6 DAC 1 BIT MUTE Block DACOUT2 5 4 DAC 2 BIT MUTE Block 3 HPOUT 2 DAC 3 Copyright © 2008, Texas Instruments Incorporated www.ti.com ...

  • Page 23

    ... M8051 MCU ROM code follows this sequence after device reset release. After Micro completes boot up application code (RAM code), the microcontroller switches the program counter from ROM to RAM code by pc_source(esfr - 0xFD). Copyright © 2008, Texas Instruments Incorporated 2 C transactions, control pin operations, and participation in most ...

  • Page 24

    ... TAS3218 www.ti.com GPIO1 = Low Load default Check GPIO 1 DAP Program and coefficient GPIO1 = High Loaded Setup Enable DAP I2C Slave I/F Processing start GPIO1 output Low Test command received Test Processing Main IDLE loop Routine 4. Copyright © 2008, Texas Instruments Incorporated ...

  • Page 25

    ... As long as the RESET pin is held a logic 0 the device is in the reset state. During this reset state, all I Serial Data bus operations are ignored. The I until device initialization has completed. Copyright © 2008, Texas Instruments Incorporated Table 4. Process Description ESFR Clear micro internal RAM (256 byte) ...

  • Page 26

    ... I Table Slave Addressing SLAVE ADDRESS CS 0x68/69 0 0x6A/6B 1 Table Master Addressing SLAVE ADDRESS CS 0xA0/A1 0 0xA2/A3 1 Product Folder Link(s): TAS3218 www.ti.com Formats interface, and start normal 2 C bus via an external address for each I C interface. Copyright © 2008, Texas Instruments Incorporated ...

  • Page 27

    ... If the GPIO ports are left in their power turn on default state, they are input ports with a weak pull-up on the input to VDSS. Copyright © 2008, Texas Instruments Incorporated 2 C interface and enable the slave I C interface and read the status register to determine the load status. ...

  • Page 28

    ... LD Reset Data Path Switch Figure 18. GPIO Ports Product Folder Link(s): TAS3218 www.ti.com GPIOMICROCOUNT GPIOMICROCOUNT GPIO_samp_int Ack Ack MS BYTE LS BYTE See Note A Reset MICRO_CLK Watchdog Timer Decode 2^16 Copyright © 2008, Texas Instruments Incorporated 0 Ack ...

  • Page 29

    ... If a subaddress assignment only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3218 as another sub address replacing the one previously written. Copyright © 2008, Texas Instruments Incorporated 2 C data to the I ...

  • Page 30

    ... Except for the last data byte, the Not Acknowledge Acknowledge Acknowledge D0 Ack Ack Ack Other Data Bytes Last Data Byte 2 C addressing. For random 2 C write transaction has taken 2 C sequential write Copyright © 2008, Texas Instruments Incorporated Stop Condition Stop Condition ...

  • Page 31

    ... At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3218 acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. Copyright © 2008, Texas Instruments Incorporated 2 C master, can execute a complete download of any internal memory or ...

  • Page 32

    ... C check sums to verify a proper EEPROM download. The 2 C check sum at sub address 0x00, is stored and NOTE: C master, the data rate transfer is fixed at 375 kHz. Product Folder Link(s): TAS3218 www.ti.com 2 C bus operations check sum and the check Copyright © 2008, Texas Instruments Incorporated ...

  • Page 33

    ... N must always be set so that the over-sample clock into the I master and slave controllers is at least a factor of 20 higher in frequency than SCL special case. When mode is enabled that detects I interface to reset and continue operation after receiving an invalid I Copyright © 2008, Texas Instruments Incorporated 2 C transactions. The TAS3218 I NOTE: ...

  • Page 34

    ... The memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM, assessable via the I 34 Submit Documentation Feedback 2 C programmable coefficients group of products 2 C bus, is available to the user. Product Folder Link(s): TAS3218 www.ti.com Copyright © 2008, Texas Instruments Incorporated ...

  • Page 35

    ... Figure 24. Arithmetic Unit Data Word Structure Rollover Figure 25. DSP ALU Operation with Intermediate Overflow Copyright © 2008, Texas Instruments Incorporated Overhead/Guard Bits 16-bit 18-bit audio 20-bit audio audio Precision/Noise Bits 8-Bit ALU Operation (without saturation) 10110111 (–73) + 11001101 (–51) 10000100 (–124) + 11010011 (– ...

  • Page 36

    ... NEG48 = 0x80_0 000_0000 _00 32-Bit Clipping POS40 = 0xXX_ 7FFF_FFFF _XX NEG40 = 0 xXX_ 8000_0000 _XX 28-Bit Clipping POS20 = 0xXXXXX_ NEG20 = 0xXXXXX_ Product Folder Link(s): TAS3218 www.ti.com 0 ... 0 15–0 27–23 22 --------------- 0 Fractional Noise 30–0 38– 7FFF_FFF 8000_000 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 37

    ... Micro 24 Mem VOL (5 LSBs) VOL LSBs) LFS 2 Barrel Shift DLYO NEG, ABS ACC 76 Operand A Delay RAM Copyright © 2008, Texas Instruments Incorporated DATA RAM 1024 24 X DATA RAM 768 LOG, ALOG, NEG, ABS, or THRU THRU Operand B ADD 76 CLIP 48 DLYI Output Register File (DO8–DO8) Figure 27 ...

  • Page 38

    ... C command(s). Eight of the pointers are used to write/retrieve 48-bit data Product Folder Link(s): TAS3218 DO5 DO6 DO7 DO8 Audio_out8 DAC Ext_mem SPDIF(L) SPDIF( DSP Coef RAM ( Data RAM (768 Memory Interface Program RAM (3 . Delay Delay Memory Control ( 17408 Copyright © 2008, Texas Instruments Incorporated www.ti.com Gen) ...

  • Page 39

    ... FIR operations as well as extending the addressable memory space. The Ext instruction bit (bit 54) has been added to extend the internal memory address space by 1 bit, increasing the memory space from words. Copyright © 2008, Texas Instruments Incorporated 55-BIT INSTRUCTION Data Memory Load ...

  • Page 40

    ... Extension bit designates offset these address references for LD/ST operations Product Folder Link(s): TAS3218 www.ti.com TAS3208 instruction word Memory Store MOP2 AD2 MOP3 AD3 26–24 23–14 13–10 9–0 Memory Store MOP2 AD2 MOP3 AD3 26–24 23–14 13–10 9–0 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 41

    ... Analog supply voltage V High-level input voltage IH V Low-level input voltage IL Operating ambient air temperature range T A (guarantying parametric) T Operating junction temperature range J Copyright © 2008, Texas Instruments Incorporated (1) 3.3-V TTL 3.3-V Analog 1.8-V LVCMOS 3.3-V TTL 3.3-V Analog 1.8-V LVCMOS (V < > DVDD < ...

  • Page 42

    ... Filter group delay 42 Submit Documentation Feedback CONDITIONS A: WTD A-WTD MIN 20 0.45 Fs 0.5501 Fs Product Folder Link(s): TAS3218 www.ti.com MIN TYP MAX UNIT TYP MAX UNIT 0 17/ 0.06 dB 0.5501 Fs Hz 7.455 Fs kHz 65 dB 21/Fs s Copyright © 2008, Texas Instruments Incorporated ...

  • Page 43

    ... When the TAS3218 is operated in slave mode, the internal analog clocks for ADC and DAC are derived from external MCLKIN input. In this case, the analog performance will depend on MCLKIN quality (i.e., jitter, phase noise, etc.). (2) 16- series resistor required in L and R headphone outputs for short-circuit protection. Copyright © 2008, Texas Instruments Incorporated (1) TEST CONDITIONS ...

  • Page 44

    ... Between each line input Full scale output voltage (0 dB) 44 Submit Documentation Feedback TEST CONDITIONS powered down GND Product Folder Link(s): TAS3218 www.ti.com MIN TYP MAX UNIT 0.81 0.9 Vrms 80 90 dBA 1.15 Vrms 1.43 1.5 1. 0.9 1 1.1 Vrms Copyright © 2008, Texas Instruments Incorporated ...

  • Page 45

    ... Frequency tolerance is 100 ppm (or better) at 25C. ( cyc1 TALI ( cyc2 MCLKIN ( cyc3 MCLKOUT (5) When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when MCLKOUT = MCLKIN. Copyright © 2008, Texas Instruments Incorporated TEST CONDITIONS 0. 0. ...

  • Page 46

    ... TEST CONDITIONS Product Folder Link(s): TAS3218 www.ti.com MIN TYP MAX UNIT 100 ms Figure 35 MIN TYP MAX UNIT 100 s 200 ns <50 ms MIN TYP MAX UNIT 32 48 kHz 0 cyc cyc 64 Fs MHz 1/ MIN TYP MAX UNIT 48 kHz MHz Copyright © 2008, Texas Instruments Incorporated ...

  • Page 47

    ... SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This f allows series protection resistors (Rs connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Copyright © 2008, Texas Instruments Incorporated TEST CONDITIONS 3.3-V TTL ...

  • Page 48

    ... Inactive tr = ~100 s µ DMSTATE 48 Submit Documentation Feedback t cyc1 tw MCLKI t cyc2 tf tw MCLKO MCLKO t cyc3 t pgw(L) Figure 34. Reset Timing During Power-On tr EMSTATE Figure 35. Reset Timing Product Folder Link(s): TAS3218 www.ti.com td MI–MO tr MCLKO Start of Boot Sequence Copyright © 2008, Texas Instruments Incorporated ...

  • Page 49

    ... SDOUT1 SDOUT2 SDIN1 SDIN2 SCLKOUT Figure 36. Serial Audio Port Slave Mode Timing Waveforms SCLKOUT LRCLKOUT SDOUT1 SDOUT2 SDIN1 SDIN2 SDIN3 Figure 37. Serial Audio Port Master Mode Timing Waveforms Copyright © 2008, Texas Instruments Incorporated tw SCLKIN t cyc su1 tf tr LRCLK, LRCLK t pd1 ...

  • Page 50

    ... If this is a termination header, this 2 byte value is 0000 Header size (12) + data byte + last 2 byte checksum byte. If this is a termination header, this value is 0000 1 byte Unused 1 byte Unused Product Folder Link(s): TAS3218 www.ti.com BUF SP t SU;STO P S NOTES Copyright © 2008, Texas Instruments Incorporated ...

  • Page 51

    ... Data byte 3 Data byte 4 (MSB) Data byte 5 (LSB) Data byte 6 16 Data byte 7 Data byte 8 (MSB) 0x00 0x00 Checksum MSB Checksum LSB Copyright © 2008, Texas Instruments Incorporated SIZE VALUE 2 byte 0x00 2 byte 0x1F 0x00 or 1 byte 0x01 1 byte 0x00 2 byte ...

  • Page 52

    ... Header (12) + data (N) + checksum (4) 1 byte 0x00 Unused 1 byte 0x00 Unused Program word 1 D7D0 D15D8 D23D16 7 byte D31D24 D39D32 D47D40 D55D48 7 byte Program word 2 Repeated checksum byte 2 7 byte through N +11 Product Folder Link(s): TAS3218 www.ti.com NOTES Copyright © 2008, Texas Instruments Incorporated ...

  • Page 53

    ... Data byte 4 (MSB) Data byte 5 (LSB) Data byte 6 16 Data byte 7 Data byte 8 (MSB) 0x00 0x00 Checksum MSB Checksum LSB Copyright © 2008, Texas Instruments Incorporated SIZE VALUE 2 byte Checksum of byte 2 through 0x00 2 byte Must be 0x001F 0x1F Micro program RAM or micro external 1 byte ...

  • Page 54

    ... D39D32 D47D40 6 byte Data word 2 Repeated checksum byte 2 through N 6 byte + master bus. The transfer is performed by writing slave download flow. Table 14 to Table Product Folder Link(s): TAS3218 www.ti.com NOTES 2 18. The I C slave download process is Copyright © 2008, Texas Instruments Incorporated ...

  • Page 55

    ... Initialize Header Information Clear Invalid Memory Select Status Num_byte termination header) YES Status Error? NO pc_source = 1 PCON = 0x01 RAM Switch Copyright © 2008, Texas Instruments Incorporated 2 Enable I C Slave Mode IDLE Invalid > 0 Mem_select Valid Status I = error Check num_byte NG Num_byte OK? OK Halt DSP ...

  • Page 56

    ... External Data RAM Block Structure CALC TOTAL CHECK NUM SUM BYTE Product Folder Link(s): TAS3218 www.ti.com (1) NOTE If the last data register datum is less than 6 byte, zero data should be filled. Should be zero End checksum is always located here Copyright © 2008, Texas Instruments Incorporated ...

  • Page 57

    ... Register 5 0x00 0x05 6 0x00 7 Checksum MSB 8 Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Copyright © 2008, Texas Instruments Incorporated CALC TOTAL CHECK NUM SUM BYTE Program word 1 Program word 2 Should be zero End checksum is always located here ...

  • Page 58

    ... Shades cells indicate the values included in the checksum/total number of bytes calculation. 58 Submit Documentation Feedback CALC TOTAL CHECK NUM SUM BYTE Coefficient word 1 Coefficient word 2 Coefficient word 3 Coefficient word 4 Coefficient word N or zero Should be zero End checksum is always located here Product Folder Link(s): TAS3218 www.ti.com (1) NOTE Copyright © 2008, Texas Instruments Incorporated ...

  • Page 59

    ... Register 5 0x00 0x05 6 0x00 7 Checksum MSB 8 Checksum LSB (1) Shades cells indicate the values included in the checksum/total number of bytes calculation. Copyright © 2008, Texas Instruments Incorporated Table 17. DSP Data Block Structure CALC TOTAL CHECK NUM SUM BYTE Product Folder Link(s): TAS3218 TAS3218 SLES235 – ...

  • Page 60

    ... Copyright © 2008, Texas Instruments Incorporated ...

  • Page 61

    ... Unused 0x3a Unused 0x3b Unused 0x3c Unused 0x3d Unused 0xfe Unused 0xff Unused Copyright © 2008, Texas Instruments Incorporated 2 Table 19 Register Map (continued) BYTES CONTENTS 4 See SPDIF Control 4 u(31:24), u(23:16), u(15:8), u(7:0) 4 u(31:24), u(23:16), u(15:8), u(7:0) 4 u(31:24), u(23:16), u(15:8), u(7:0) ...

  • Page 62

    ... DESCRIPTION Unused Clock master/slave select Unused SAP output normalization Unused Digital audio output word size Unused Digital audio input word size Unused Digital audio output format Unused Digital audio input format (1) CMS (1) IW0/OW0 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 63

    ... D40D32 of this register. BIT BIT BIT BIT BIT BIT BIT BIT ABSY Copyright © 2008, Texas Instruments Incorporated Table 24. Audio Data Format IM1/OM1 Left-justified 0 Right-justified Table 25. SAP/Clock Setting Micro program memory load error Micro external memory load error ...

  • Page 64

    ... I C BUS ERROR BUSE Bus error 1 No bus error 0 (1) Default values are shown in italics registers. The first register is a eight byte register than holds the NOTE: Product Folder Link(s): TAS3218 www.ti.com ABSY bus error Copyright © 2008, Texas Instruments Incorporated ...

  • Page 65

    ... BIT BIT Copyright © 2008, Texas Instruments Incorporated SIZE 2 bytes 1 byte 1 byte 2 bytes 2 bytes 24-BIT DATA 28-BIT DATA XXXX D27D24 D23D16 D15D8 D7D0 XXXX D27D24 D23D16 D15D8 D7D0 (Table 31) allow the user to access the internal resources of TAS3218 DSP coefficient memory load error ...

  • Page 66

    ... Data to be read or written Data to be read or written Data to be read or written ACK address (LS Byte) D47–D40 ACK D39–D32 ACK D15–D8 D7–D0 ACK D47–D40 D39–D32 ACK D15–D8 D7–D0 Copyright © 2008, Texas Instruments Incorporated ACK P ACK NAK P ACK NAK P ...

  • Page 67

    ... BIT GPIOMICROCOUNT sets the number of micro clock cycles for Timer 0 interrupt. In Timer 0 interrupt service routine, watchdog timer is reset enabled. The default value for this counter is 0x5820 which correspond to a period 1.25 ms. Copyright © 2008, Texas Instruments Incorporated Table 32. Mute Control ...

  • Page 68

    ... POWERDOWN Powerdown and disable Powerup and enable Product Folder Link(s): TAS3218 www.ti.com DESCRIPTION Unused Unused Unused DIT reset DAC3 (HPOUT) DAC2 (DACOUT2) DAC1 (DACOUT1) AMUX + AAF + ADC AMUX3 + Line Amp 3 AMUX2 + Line Amp 2 AMUX1 + LineAmp1 Copyright © 2008, Texas Instruments Incorporated ...

  • Page 69

    ... A-MUX Control (0x12) BIT BIT BIT Copyright © 2008, Texas Instruments Incorporated Table 39. A-MUX Control (0x12 Product Folder Link(s): TAS3218 TAS3218 SLES235 – JULY 2008 DESCRIPTION Reserved Reserved Reserved Reserved DAC Analog MUX line 10 select Analog MUX line 9 select Analog MUX line 8 select ...

  • Page 70

    ... Analog MUX line 9 select Analog MUX line 8 select Analog MUX line 7 select Analog MUX line 6 select Analog MUX line 5 select Analog MUX line 4 select Analog MUX line 3 select Analog MUX line 2 select Analog MUX line 1 select MUTE Copyright © 2008, Texas Instruments Incorporated ...

  • Page 71

    ... SR b24 b25 0 VL BIT Cat Cat Cat b8 b9 b10 BIT (1) Default values are shown in italics. (1) Default values are shown in italics. SAMPLING RATE Copyright © 2008, Texas Instruments Incorporated Table 40. PDIF Control (0x16 b29 WL3 WL2 WL1 WL0 SRC# SRC# SRC# SRC# ...

  • Page 72

    ... DC Dither Enable DC DITHER ENABLE ON Disable 0 Enable 1 (1) Default values are shown in italics Product Folder Link(s): TAS3218 b18 b17 b16 b11 b12 b13 b14 (1) MUX2 0 1 DESCRIPTION Unused Unused Unused Unused DC dither enable DESCRIPTION Unused Copyright © 2008, Texas Instruments Incorporated www.ti.com ...

  • Page 73

    ... Table 52. DSP Program Start Address (0x1e) (continued) BIT BIT BIT Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218 TAS3218 SLES235 – JULY 2008 DESCRIPTION Unused Starting address MSB Starting address LSB Submit Documentation Feedback 73 ...

  • Page 74

    ... Line 33K 4.7uF 56 33K 4.7uF Line Line 33K 4.7uF 53 AVDD_LI 33K 4.7uF Line Line 33K 4.7uF 4.7uF 1 2 Line 4.7uF 1 2 Line 4.7uF 1 2 Line 4.7uF 1 2 Line 4.7uF 1 2 Line 4.7uF 1 2 Line Copyright © 2008, Texas Instruments Incorporated www.ti.com ...

  • Page 75

    ... Orderable Device Status TAS3218IPZP ACTIVE TAS3218IPZPR ACTIVE TAS3218PZPR ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...

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