TAS5028APAGG4

TAS5028 8 Channel Digital Audio PWM Processor 2004 Data Manual DAV-Digital Audio/Speaker TM SLES112 ...

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Section 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Contents 2.3.7 Inter-channel Delay 2.4 Master Clock and Serial Data Rate Controls 2.4.1 PLL Operation 2.5 Bank Controls . . . . . . . . . . . . . . . . . . . . . . ...

Automute Control Register(0x14) 6.11 Automute PWM Threshold and Backend Reset Period (0x15) 6.12 Modulation Index Limit Register (0x16) 6.13 Interchannel Channel Delay Registers (0x1B - 0x22) and Offset Register (0x23) 6.14 Bank Switching Command (0x40) 6.15 Input Mixer Registers ...

... Device Outputs During Power Down 2-4 Device Outputs During Backend Error 2-5 Description of the Channel Configuration Registers (0x05 to 0x0C) 2-6 Recommended TAS5028 Configurations for Texas Instruments Power Stages 2-7 Audio System Configuration (General Control Register 0xE0) 2-8 Volume Ramp Rates in ms ...

Output Mixer Control (Lower 4 Bytes) 6-20 Output Mixer Control (Upper 4 Bytes) 6-21 Output Mixer Control (Middle 4 Bytes) 6-22 Output Mixer Control (Lower 4 Bytes) 6-23 Volume Gain Update Rate (Slew Rate) 6-24 Treble and Bass Gain ...

List of Tables viii SLES112 May 2004 ...

... This enables the TAS5028 to provide an easy to use control interface with relaxed timing requirements. The TAS5028 can drive eight channels of H-bridge power stages. Texas Instruments H-bridge parts TAS5111, TAS5112, or TAS5182 + FETs are designed to work seamlessly with the TAS5028. The TAS5028 supports both single-ended or bridge tied load configurations ...

... RIGHT BACK LEFT BACK SURROUND SURROUND - + + TAS5121 TAS5121 Lineout Right PWM to Analog Lineout Left (Line Level) Figure Recommended TAS5028 + TAS5121 Channel Configuration 2 TAS5028 AM Texas Instruments FM Digital Audio Amplifier Tuner MPEG Decoder Front-Panel Controls SUBWOOFER CENTER RIGHT LEFT SURROUND SURROUND - - - - + ...

TAS5028 Features 1.2.1 Audio Input / Output • Automatic Master Clock Rate and Data Sample Rate Detection • Eight Serial Audio Input Channels • Eight PWM Audio Output Channels Configurable as Six Channels With Stereo Line Out or Eight ...

Introduction 1.2.3 PWM Processing • 32-Bit Processing PWM Architecture With 40 Bits of Precision • 8x Oversampling With 5 and 2x Oversampling at 176.4 kHz and 192 kHz • >102-dB Dynamic Range • THD+N < 0.1% • 20 – 20-kHz ...

Physical Characteristics 1.3.1 Terminal Assignments VRA_PLL 1 PLL_FLT_RET 2 PLL_FLTM 3 PLL_FLTP 4 AVSS 5 AVSS 6 VRD_PLL 7 AVSS_PLL 8 AVDD_PLL 9 VBGAP 10 RESET 11 HP_SEL 12 PDN 13 MUTE 14 DVDD 15 DVSS 16 1.3.2 Ordering ...

Introduction TERMINAL 5-V 5-V I/O I/O TOLERANT TOLERANT NO. NAME 7 VRD_PLL P 8 AVSS_PLL P 9 AVDD_PLL P 10 VBGAP P 11 RESET HP_SEL PDN MUTE DI ...

TERMINAL 5-V 5-V I/O I/O TOLERANT TOLERANT NO. NAME 28 SDIN4 SDIN3 SDIN2 SDIN1 RESERVED O 33 VR_DIG P 34 DVSS P 35 DVSS ...

Introduction TERMINAL 5-V 5-V I/O I/O TOLERANT TOLERANT NO. NAME 63 MCLK RESERVED NOTES: 1. Type analog 3.3-V digital power / ground / decoupling input output ...

Serial Audio Interface The TAS5028 operates as a slave only / receive only serial data interface in all modes. The TAS5028 has four PCM serial data interfaces to permit eight channels of digital data to be received though the ...

Introduction The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section. The DAP supports two configurations, one for 32-kHz – 96-kHz data and one for 176.4-kHz to 192-kHz data. 1.4.5.1 TAS5028 ...

Table TAS5028 Audio Processing Feature Sets kHz FEATURE 8 CHANNEL FEATURE SET Signal processing channels Pass through channels Master volume 1 for eight channels Individual channel volume controls Four Bass and Treble tone controls ...

Introduction Default Input Is BOLD SDIN1 - L( SDIN1 - R ( SDIN2 - L (LS Mixer SDIN2 - R (RS (I2C 0x41) SDIN3 - L (LBS) F ...

Default input is BOLD SDIN1 SDIN1 - R ( SDIN2 - L (LS Mixer SDIN2 - R (RS (I2C 0x41) SDIN3 - L (LBS ...

Introduction A_to_ipmix Left A SDIN1 B Right B_to_ipmix C_to_ipmix Left C SDIN2 Input Mixer D Right D_to_ipmix E_to_ipmix Left E SDIN3 F Right F_to_ipmix G_to_ipmix Left G SDIN4 H Right H_to_ipmix Figure TAS5028 Detailed Channel Processing 2 ...

The decimal value of a 5.23 format number can be found by following the weighting shown in Figure the most significant bit is logic 0, the number is a positive number, and the weighting shown yields ...

Introduction - 23 2 Bit - 10 2 Bit - 1 2 Bit 0 2 Bit 16 2 Bit 22 2 Bit 23 2 Bit Sign Bit S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx Figure shows the derivation of the decimal value of ...

Coefficient Coefficient Coefficient Digit 16 Digit 15 Digit 14 Integer Digit 4 0 (Bit 2 ) Integer Integer Digit 5 Digit ...

Introduction Similarly, the TAS5028 carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5028 advanced digital audio processor achieves both of these important performance capabilities ...

Table Bass and Treble Filter Selections FS (kHz) FILTER FILTER FILTER SET 1 SET 1 SET 2 BASS TREBLE BASS 32 42 917 1088 99 44.1 57 1263 115 48 63 1375 125 88.2 ...

Introduction 1.8.1 Auto Mute and Mute The TAS5028 has individual channel automute controls that are enabled via the I separate detectors used to trigger the automute: • Input Auto Mute: All channels are muted when all 8 inputs to the ...

Select Output N Select Output N Select Output N Select Output N Select Output N 1.10 PWM The TAS5028 has eight channels of high performance digital PWM Modulators that are designed to drive switching output stages (backends) in both single-ended ...

... Figure 1 - 17. De-emphasis Filter Characteristics 1.10.3 AM Interference Avoidance Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments patented AM interference avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5028 adjusts the radiated emissions to provide an emission clear zone for the tuned AM frequency ...

Analog Receiver Figure 1 - 18. Block Diagrams of Typical Systems Requiring TAS5028 Automatic AM Interference SLES112 — June 2004 ADC Audio TAS5508 PCM1802 DSP Audio DSP provides the master and bit clocks Audio Digital TAS5508 Receiver DSP The Digital ...

Introduction 24 TAS5028 SLES112 — June 2004 ...

TAS5028 Controls and Status The TAS5028 provides control and status information from both the I This section describes some of these controls and status functions. The I descriptions are contained in sections at the end of this document. 2 ...

TAS5028 Controls and Status Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational state is performed ...

After the initialization time, the TAS5028 starts the transition to the operational state with the Master volume set at mute. Since the TAS5028 has an external crystal time base, following the release of RESET, the TAS5028 sets the MCLK and ...

TAS5028 Controls and Status Table Device Outputs During Backend Error SIGNAL PWM P-outputs PWM M-outputs HPPWM P-outputs HPPWM M-outputs 2.2.4 Speaker / Headphone Selector (HP_SEL) The HP_SEL terminal enables the headphone output or the speaker outputs. The ...

... This bit sets the PWM outputs high-high during mute. D0 Not used Table lists the optimal setting for each output stage configuration. Note that the default value is applicable in all configurations except the TAS5182 SE/BTL configuration. Table Recommended TAS5028 Configurations for Texas Instruments Power Stages DEVICE ERROR RECOVERY Default RES ...

TAS5028 Controls and Status 2.3.3 Audio System Configurations The TAS5028 can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system and 8-channel system. The audio system configuration is set in the General Control Register (0xE0). ...

... This is also the default setting of the TAS5028. Default settings can be changed in the Modulation Index Register (0x16). Note that no change should be made to this register when using Texas Instruments power stages. 2.3.7 Inter-channel Delay An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per channel from 0 to 255 clock cycles ...

TAS5028 Controls and Status This delay is generated in the PWM and can be changed at any time through the serial control interface I registers 0x1B – 0x22. The absolute offset for channel 1 is set in I NOTE:If used ...

Manual Bank Selection The three bank selection bits of the bank control register allow the appropriate bank to be manually selected (000 = Bank 1, 001 = Bank 2, 010 = Bank 3). In the manual mode, when a ...

TAS5028 Controls and Status Strategy: Use the TAS5028 bank switching feature to allow for managing and switching three banks associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3). One possible ...

Electrical Specifications 3.1 Absolute Maximum Ratings Supply voltage, DVDD and DVD_PWM Supply voltage, AVDD_PLL 3.3-V digital input ( tolerant digital input Input voltage Input voltage (3) 1.8 V LVCMOS Input clamp current < ...

Electrical Specifications 3.4 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER V V High-level output voltage High level output voltage Low level output voltage Low-level output voltage OL I High-impedance output current ...

Serial Audio Port 3.6.2.1 Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER f Frequency, SCLK SCLKIN t Setup time, LRCLK to SCLK rising edge su1 t Hold time, LRCLK from SCLK ...

Electrical Specifications 2 3.6 Serial Control Port Operation 3.6.3.1 Timing Characteristics for I Conditions (Unless Otherwise Noted) PARAMETER f Frequency, SCL SCL t Pulse duration, SCL high w(H) t Pulse duration, SCL low w(L) t Rise time, SCL ...

Reset Timing (RESET) 3.6.4.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) t Time to M-STATE low r(DMSTATE) t Pulse duration, RESET active w(RESET Time to enable I C r(I2C_ready) t Device startup time r(run) ...

Electrical Specifications 3.6.6 Backend Error (BKND_ERR) 3.6.6.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) t Pulse duration, BKND_ERR active w(ER) t p(valid_low programmable to be between p(valid_high) ERR_RCVRY M-State ...

Headphone Select (HP_SEL) 3.6.8.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER t Pulse duration, HP_SEL active w(MUTE) t Soft volume update time d(VOL) t Switch-over time (SW) NOTE 2: See the Volume Treble and Base ...

Serial Audio Interface Control and Timing 3.6.9 Volume Control 3.6.9.1 Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER Maximum attenuation before mute Maximum gain Maximum volume before the onset of clipping 3.7 Serial Audio Interface Control and ...

Left Justified Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high for the left channel and low ...

Serial Audio Interface Control and Timing 3.7.3 Right Justified Right justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is high ...

I C Serial Control Interface (Slave Address 0x36) The TAS5028 has a bidirectional I both 100 Kbps and 400 Kbps data transfer rates for single and multiple byte write and read operations. This is a slave only device ...

I C Serial Control Interface (Slave Address 0x36) Supplying a subaddress for each subaddress transaction is referred to as random I TAS5028 also supports sequential I by data for that subaddress and the fifteen subaddresses that follow, a sequential ...

When the correct number of bytes has been received, the TAS5028 starts processing the data. The procedure to perform an incremental multi-byte write operation is as follows Start a normal I C write operation by sending the device ...

I C Serial Control Interface (Slave Address 0x36) 48 TAS5028 SLES112 — June 2004 ...

Serial Control I C Register Summary The TAS5028 slave address is 0x36. See the Serial Control I bit definitions. Note that u indicates unused bits TOTAL REGISTER FIELDS SUBADDRESS BYTES 0x00 1 Clock control register ...

Serial Control I C Register Summary TOTAL REGISTER FIELDS SUBADDRESS BYTES 0x1B–0x22 1/Reg. Inter-channel delay registers 0x23 1 Inter-channel offset 0x24- 0x3F 0x40 4 Bank switching command register See the Input Mixer Registers 0x41–0x48 32/Reg (0x41 ...

I C TOTAL REGISTER FIELDS SUBADDRESS BYTES 0xD5 4 Ch5 volume 0xD6 4 Ch6 volume 0xD7 4 Ch7 volume 0xD8 4 Ch8 volume 0xD9 4 Master volume OXDA 4 Bass filter set ( 0xDB 4 Bass filter ...

Serial Control I C Register Summary 52 TAS5028 SLES112 — June 2004 ...

Serial Control Interface Register Definitions Unless otherwise noted, the I Note that u indicates unused bits. 6.1 Clock Control Register (0x00) Bit D1 is Don’t Care ...

Serial Control Interface Register Definitions 6.4 System Control Register 1 (0x03) Bit D5, D2, D1, and D0 are Don’t Care ...

Headphone Configuration Control Register (0x0D) Bit D0 is Don’t Care. Table Headphone Configuration Control Register ...

Serial Control Interface Register Definitions 6.9 Soft Mute Register (0x0F ...

Automute PWM Threshold and Backend Reset Period (0x15) Table 6 - 11. Automute PWM Threshold and Backend Reset Period ...

Serial Control Interface Register Definitions 6.13 Interchannel Channel Delay Registers (0x1B - 0x22) and Offset Register (0x23) Channels and 8 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22). Bits ...

Bank Switching Command (0x40) Bits D31 - D24, D22 - D19 are Don’t Care. D31 D30 D29 D28 D23 D22 D21 D20 - - - - - - - D15 D14 D13 D12 ...

Serial Control Interface Register Definitions 6.15 Input Mixer Registers (0x41 – 0x48, Channels Input mixers and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48. ...

I C TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[3] B_to_ipmix[3] C_to_ipmix[3] D_to_ipmix[3] 0x43 0x43 32 32 E_to_ipmix[3] F_to_ipmix[3] G_to_ipmix[3] H_to_ipmix[3] A_to_ipmix[4] B_to_ipmix[4] C_to_ipmix[4] D_to_ipmix[4] 0x44 0x44 32 32 E_to_ipmix[4] F_to_ipmix[4] G_to_ipmix[4] H_to_ipmix[4] A_to_ipmix[5] B_to_ipmix[5] C_to_ipmix[5] D_to_ipmix[5] 0x45 0x45 32 32 ...

Serial Control Interface Register Definitions TOTAL REGISTER SUBADDRESS BYTES FIELDS A_to_ipmix[6] B_to_ipmix[6] C_to_ipmix[6] D_to_ipmix[6] 0x46 0x46 32 32 E_to_ipmix[6] F_to_ipmix[6] G_to_ipmix[6] H_to_ipmix[6] A_to_ipmix[7] B_to_ipmix[7] C_to_ipmix[7] D_to_ipmix[7] 0x47 0x47 32 32 E_to_ipmix[7] F_to_ipmix[7] G_to_ipmix[7] H_to_ipmix[7] A_to_ipmix[8] B_to_ipmix[8] C_to_ipmix[8] ...

Bass and Treble Bypass Register (0x89 – 0x90, Channels Channels and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C,0x8D, 0x8E, 0x8F, and 0x90. Eight bytes are written for ...

Serial Control Interface Register Definitions Table 6 - 19. Output Mixer Control (Lower 4 Bytes) D31 D30 D29 D28 D27 D26 ...

Table 6 - 21. Output Mixer Control (Middle 4 Bytes) D31 D30 D29 D28 D27 D26 ...

Serial Control Interface Register Definitions Table 6 - 24. Treble and Bass Gain Step Size (Slew Rate ...

Table 6 - 26. Master and Individual Volume Controls VOLUME INDEX (H) 6.21 Bass Filter Set Register (0xDA) Bits D31 - D27, D23 - D19, D15 - D11, and are Don’t Care. D31 D30 D29 D28 D27 ...

Serial Control Interface Register Definitions Table 6 - 28. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and Left Surround in Eight Channel Configuration) D23 D22 D21 D20 D19 D18 ...

TREBLE INDEX VALUE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 6.23 Treble Filter Set Register (0xDC) Bits D31 - D27 are Don’t Care. D31 D30 D29 D28 D27 ...

Serial Control Interface Register Definitions Table 6 - 35. Channel 4 and 3 (Right and Left Rear) D15 D14 D13 D12 D11 D10 ...

AM Mode Register (0xDE) Bits D31 - D21 are Don’t Care. D31 D30 D29 D28 D27 D26 D23 D22 D21 D20 D19 D18 ...

Serial Control Interface Register Definitions 72 TAS5028 SLES112 — June 2004 ...

TAS5028 Example Application Schematic The following page contains an example application schematic for the TAS5028. SLES112 - June 2004 TAS5028 Example Application Schematic TAS5028 73 ...

Phono socket J950 LINE OUTPUT Phono socket J951 GND J900 4 3 HEADPHONE OUTPUT 2 1 Mini-Jack (3.5mm) C C10 R10 R11 10nF 200R 200R C11 C12 100nF ...

PACKAGING INFORMATION (1) Orderable Device Status TAS5028PAG ACTIVE TAS5028PAGG4 ACTIVE TAS5028PAGR ACTIVE TAS5028PAGRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be ...

TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TAS5028PAGR TQFP PAG PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 64 1500 330.0 24.4 13.0 Pack Materials-Page 1 19-Mar-2008 ...

Device Package Type TAS5028PAGR TQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PAG 64 1500 Pack Materials-Page 2 19-Mar-2008 Width (mm) Height (mm) 346.0 346.0 41.0 ...

PAG (S-PQFP-G64) 0, 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...