IC DGTL AUDIO PROCESSOR 100-TQFP

 

TAS3218IPZP

Manufacturer Part NumberTAS3218IPZP
DescriptionIC DGTL AUDIO PROCESSOR 100-TQFP
ManufacturerTexas Instruments
TypeAudio Processor
TAS3218IPZP datasheets

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Specifications of TAS3218IPZP

ApplicationsAudio routing, processingMounting TypeSurface Mount
Package / Case100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-23686  
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TAS3218
SLES235 – JULY 2008
.......................................................................................................................................................................................................
The memory load information starts with reading the header and data information that starts at sub-address 0 of
the EEPROM. This information must be stored in a sequential memory addresses with no intervening gaps. The
Data block is contiguous blocks of data that immediately follow the headers locations. The TAS3218 memory
data can be stored and loaded in (almost) any order. Additionally this addressing scheme permits portions of the
TAS3218 internal memories to be loaded.
The TAS3218 will sequentially read EEPROM memory and load its internal memory unless it does not find a
valid memory header block, is not able to read the next memory location because the end of memory was
reached, detects a check sum error, or reads a end of program header block. When it encounters a valid header
or read error, the TAS3218 will attempt to read the header or memory location three times before it determines
that it has an error. If the TAS3218 encounters a Check Sum error it will attempt to re-read the entire block of
memory two more times before it determines that it has an error.
Once the micro program memory has been loaded, it can not be reloaded until the
TAS3218 has been RESET.
If an error is encountered TAS3218 terminates its memory load operation, loads the default configuration for both
the M8051 MCU and DSP from the embedded ROM, and disables further master I
If an end of program data block is read, the TAS3218 has completed the initial program load.
2
The I
C master mode utilizes the starting and ending I
first 16-bit data word received from the EEPROM is the I
compared against the 16-bit data word received for last subaddress, the ending I
sum that is computed during the download. These three values must be equal. If the read and computed values
do not match, the TAS3218 sets the memory read error bits in the Status register and repeats the download from
the EEPROM two more times. If the comparison check again fails the third time, the TAS3218 sets the micro
program to the default value.
2
When acting as an I
32
Submit Documentation Feedback
I2C EEPROM Memory Map
Block Header 1
Data Block 1
Block Header 2
Data Block 2
…
Block Header N
Data Block N
Figure 23. EEPROM Address Map
NOTE:
2
C check sums to verify a proper EEPROM download. The
2
C check sum at sub address 0x00, is stored and
NOTE:
C master, the data rate transfer is fixed at 375 kHz.
Product Folder Link(s):
TAS3218
www.ti.com
2
C bus operations.
2
C check sum and the check
Copyright © 2008, Texas Instruments Incorporated

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