TAS3218IPZP | |
|---|---|
| Manufacturer Part Number | TAS3218IPZP |
| Description | IC DGTL AUDIO PROCESSOR 100-TQFP |
| Manufacturer | Texas Instruments |
| Type | Audio Processor |
| TAS3218IPZP datasheets |
|
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Warranty: 60 days
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Specifications of TAS3218IPZP | |||
|---|---|---|---|
| Applications | Audio routing, processing | Mounting Type | Surface Mount |
| Package / Case | 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
| Other names | 296-23686 | ||
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SPDIF INTERFACE SIGNALS TIMING CHARACTERISTICS
PARAMETER
Fs
Encoded data sampling rate
R
SPDIF signal bitrate
spdif
UI
Unit interval
T
/T
Low/high periods
LO
HI
V
High-level output voltage
OH
V
Low-level output voltage
OL
2
I
C INTERFACE AND I/O CHARACTERISTICS OF THE SDA AND SCL BUS LINES FOR
STANDARD- AND FAST-MODE I
See
Figure 38
PARAMETER
f
SCL clock frequency
SCL
Hold time (repeated) START condition. After this period,
t
HD;STA
the first clock pulse is generated.
t
LOW period of the SCL clock
LOW
tHI
HIGH period of the SCL clock
GH
t
Set-up time for a repeated START condition
su;STA
t
Data set-up time
su;DAT
t
Rise time of both SDA and SCL signals
r
t
Fall time of both SDA and SCL signals
f
t
Set-up time for STOP condition
su;STO
t
Bus free time between a STOP and START condition
BUF
C
Capacitive load for each bus line
b
Noise margin at the LOW level for each connected device
V
nL
(including hysteresis)
Noise margin at the HIGH level for each connected device
V
nH
(including hysteresis)
V
Hysteresis of Schmitt trigger inputs
hys
Pulse width of spikes which must be suppressed by the
t
SP
input filter
Input current each I/O pin with an input voltage between
I
i
0.1 V
and 0.9 V
max
DD
DD
C
Capacitance for each I/O pin
i
Output fall time from V
min to V
IH
t
of
capacitance from 10 pF to 400 pF
2
(1) In Master mode the maximum I
C clock rate is 375 kHz.
2
(2) A Fast-mode I
C bus device can be used in a Standard-mode I
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line.
(3) C
= total capacitance of one bus line in pF.
b
(4) I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if V
(5) The maximum t
for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This
f
allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the
maximum specified tf.
Copyright © 2008, Texas Instruments Incorporated
TEST CONDITIONS
3.3-V TTL, I
= 4 mA
OH
3.3-V TTL, I
= 4 mA
OL
2
C BUS DEVICES
STANDARD MODE
MIN
0
4
4.7
4
4.7
250
4
4.7
0.1 V
DD
0.2 V
DD
10
max with a bus
IL
2
C bus system, but the requirement t
is switched off.
DD
Product Folder Link(s):
TAS3218
TAS3218
SLES235 – JULY 2008
MIN
TYP
MAX
UNIT
32
48
kHz
128 Fs
MHz
1/R
ns
spdif
1 UI
3 UI
ns
2.4
V
0.5
V
FAST MODE
UNIT
MAX
MIN
MAX
(1)
100
0
400
kHz
0.6
1.3
0.6
0.6
(2)
100
ns
(3)
1000
20 + 0.1 C
300
ns
b
(3)
300
20 + 0.1 C
300
ns
b
0.6
1.3
400
400
pF
0.1 V
DD
0.2 V
DD
0.05 V
DD
0
50
ns
(4)
(4)
10
10
10
10
10
pF
(5)
(3)
(5)
250
7 + 0.1 C
250
ns
b
250 ns must then be met.
SU;DAT
Submit Documentation Feedback
s
s
s
s
s
s
V
V
V
A
47
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