IC DSP IN-CAR REMOTE AMP 44-LQFP

TDA7502

Manufacturer Part NumberTDA7502
DescriptionIC DSP IN-CAR REMOTE AMP 44-LQFP
ManufacturerSTMicroelectronics
TypeAudio Processor
TDA7502 datasheet
 


Specifications of TDA7502

ApplicationsAutomotive SystemsMounting TypeSurface Mount
Package / Case44-LQFPDevice Core Size24b
FormatFixed PointClock Freq (max)50MHz
Mips50Device Input Clock Speed50MHz
Ram Size6KBOperating Supply Voltage (typ)3.3V
Operating Supply Voltage (min)3.15VOperating Supply Voltage (max)3.45V
Operating Temp Range-40C to 125COperating Temperature ClassificationAutomotive
MountingSurface MountPin Count44
Package TypeLQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
24-Bit fixed-point dsp core delivering up to 50
MIPS
2 x 1024 x 24 Bit of RAM for X and Y data
memory.
3072 x 24 Bit of RAM for program also usable
for delay
Serial audio interface.
Debug port.
Control interface for external GPIOs, interrupts,
and reset.
2
SPI and I
C for communication between
external micro and DSP. Both master and
slave operating modes.
PLL clock oscillator
5V-tolerant 3.3V I/O interface
Description
This device is a high-performance, fully
programmable DSP, suitable for a wide range of
applications and particularly for audio and sound
processing. It contains a 24-bit 50 MIPS DSP
core, several interfaces for control and data, plus
a configurable PLL.
Order codes
Part numbers
TDA7502
TDA7502013TR
November 2006
In-car remote amplifier DSP
LQFP44 (10x 10x 1.4mm)
The computational power and the memory
configuration make this device particularly
suitable for in car equalisation. This device will
offer the best trade-off between performance and
cost when coupled with the TDA7535, or other
devices of the same family. A library of sound
processing functions is available for this device;
some of these functions are: parametric equaliser,
cross over filters, acoustic delay, dynamic
compression, vol/bass/treble/fader, active
equalisation, Stereo spatial enhancement and
more.
Package
LQFP44 (10x 10x 1.4mm)
LQFP44 (10x 10x 1.4mm)
Rev 11
TDA7502
Packing
Tube
Tape and Reel
1/25
www.st.com
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TDA7502 Summary of contents

  • Page 1

    ... Stereo spatial enhancement and more. Package LQFP44 (10x 10x 1.4mm) LQFP44 (10x 10x 1.4mm) Rev 11 TDA7502 Packing Tube Tape and Reel 1/25 www.st.com 1 ...

  • Page 2

    ... Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 1024 x 24-Bit X-RAM (XRAM 1024 x 24 Bit Y-RAM (YRAM 3072 X 24-Bit Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 512 x 24-Bit Bootstrap ROM (Boot ROM Serial audio interface (SAI Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TDA7502 ...

  • Page 3

    ... TDA7502 List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Thermal data Table 4. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 9. Low voltage TTL interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 10. DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 11 ...

  • Page 4

    ... Figure 13. Debug port read timing Figure 14. Debug port DBCK next command after read register timing Figure 15. Definition of timing for the I Figure 16. Application schematic for TDA7502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 17. Block diagram of car amplifier audio sub-system Figure 18. TQFP44 (10x10) mechanical data & package dimensions 4/ bus ...

  • Page 5

    ... TDA7502 1 Block diagram and PIN description Figure 1. Block diagram SDI0 LRCLKT SCKT LRCLKR SCKR SCL SDA SS SCK MISO MOSI GPIO3 GPIO4 GPIO5 DBCK/GPIO1 DBIN/GPIO2 Figure 2. Pin connection (Top view) SDI1 SDI2 SDO0 SDO1 SDO2 SERIAL AUDIO INTERFACE INTERFACE SPI INTERFACE GPIO ...

  • Page 6

    ... DBSEL pin will be reset. P – 3.3V supply. G – Ground. I – SDI0 is a stereo digital audio data input pin channel 0. I – SDI1 is a stereo digital audio data input pin channel 1. I – SDI2 is a stereo digital audio data input pin channel 2. TDA7502 Function ...

  • Page 7

    ... TDA7502 Table 1. Pin description (continued) N. Name 23 LRCKR 24 SCKR 25 VDD4 26 GND4 27 SDO0 28 SDO1 29 SDO2 30 VDD5 31 GND5 32 LRCKT 33 SCKT 34 SCL 35 SDA 36 SCK MOSI 39 MISO 40 VDD6 41 GND6 42 GPIO3 43 GPIO4 44 GPIO5 1. XTI and XTO are not 5V tolerant Reset Type status I/O – Left-right clock for SAI Receiver. Master or slave. ...

  • Page 8

    ... Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Test condition Test condition @3.3V and T =125°C j Test condition @3.3V and T = 125°C j TDA7502 Value Unit -0.5 to 4 +0. 6.5 V -40 to 125 °C -55 to 150 ° ...

  • Page 9

    ... TDA7502 Table 7. Oscillator characteristics Symbol Parameter F Max oscillator frequency (XTI) osc Table 8. General interface electrical characteristics Symbol Parameter Low level input current without l il pullup device High level input current without l ih pullup device Tri-state output leakage without I oz pull up/down device ...

  • Page 10

    ... Electrical specifications Figure 3. Maximum DSP clock frequency (F MHz MHz MHz 10/25 ) versus junction temperature (T dsp Vdd = 3.3V -40 25 Vdd = 3.15V -40 25 Vdd = 3.45V -40 25 TDA7502 125 Temp 125 Temp 125 Temp ) j ...

  • Page 11

    ... TDA7502 3 SAI interface Figure 4. SAI timings SDI0-3 LRCKR SCKR (RCKP=0) Table 11. Cycles Timing t Minimum Clock Cycle sckr t SCKR active edge to data out valid dt t LRCK setup time lrs t LRCK hold time lrh t SDI setup time sdid t SDI hold time sdih t Minimum SCK high time ...

  • Page 12

    ... SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. LRCKR (#23) SCKR (#24) SDI0,1,2 (#20, #21, #22) Figure 8. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. LRCKR (#23) SCKR (#24) SDI0,1,2 (#20, #21, #22) 12/25 LEFT MSB(n-1) LSB(word n) LEFT LSB(n-1) MSB(word n) LEFT LSB(n-1) MSB(word n) RIGHT LSB+1 (n) LSB+2 (n) D02AU1359 RIGHT MSB-1 (n) MSB-2 (n) D02AU1360 RIGHT MSB-1 (n) MSB-2 (n) D02AU1361 TDA7502 ...

  • Page 13

    ... TDA7502 4 SPI interfaces Table 12. SPI interfaces Symbol Master t Clock cycle sclk t Sclk edge to MOSI valid dtr t MISO setup time misosetup t MISO hold time misohold t SCK high time sclkh t SCK high low sclkl Slave t Clock cycle sclk t Sclk edge to MOSI valid dtr ...

  • Page 14

    ... Last DBCK low to DBOUT invalid (Hold) DBSEL setup to DBCK Figure 10. Debug port serial clock timing. DBCK (input) Figure 11. Debug port acknowledge timing. DBRQN (input) DBOUT (output) 14/25 Characteristics (1) (3) (5) (6) D02AU1364 TDA7502 dclk = 40MHz Unit Min. Max 200 -- ns ...

  • Page 15

    ... TDA7502 Figure 12. Debug port data I/O to status timing. DBCK (input) DBOUT (output) DBIN (input) Figure 13. Debug port read timing. DBCK (input) DBOUT (output) Note: 1 High Impedance, external pull-down resistor Figure 14. Debug port DBCK next command after read register timing. DBCK (input) ...

  • Page 16

    ... C bus. t SU:STA HD:DAT HIGH SU:DAT Standard mode 2 Test condition I Min. 0 4.7 4.0 4.7 4.0 4 – – 4 250 – TDA7502 HD:STA SU:STO D02AU1371 Fast mode bus C bus Max. Min. Max. 100 0 400 – 1.3 – – 0.6 – – 1.3 – – ...

  • Page 17

    ... TDA7502 6 Functional description The TDA7502 contains one DSP core and associated peripherals. 6.1 24-BIT DSP core. The DSP core is used to process the converted analog audio data coming from the CODEC chip via the SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP ...

  • Page 18

    ... Spare space in the program area may be used as data memory to implement delay lines for example. 6.3.4 512 x 24-Bit Bootstrap ROM (Boot ROM) This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the DSP. 18/25 2 C). TDA7502 ...

  • Page 19

    ... TDA7502 Essentially this consists of a routine that is called when the DSP comes out of reset. There are four different boot modes supported by the boot ROM. The first mode loads the application program via SPI interface where Casper’s SPI is in master mode. The second boot mode enables the debug port and waits ...

  • Page 20

    ... The clocks to the DSP can be selected to be either the VCO output divided 16 driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0). 20/ bus has its own unique address whether CPU, TDA7502 ...

  • Page 21

    ... TDA7502 7 Application scheme Figure 16. Application schematic for TDA7502 Application scheme SCKT LRCKT GND5 VDD5 SDO2 SDO1 SDO0 GND4 VDD4 SCKR LRCKR SDI2 SDI1 SDI0 21/25 ...

  • Page 22

    ... Application scheme Figure 17. Block diagram of car amplifier audio sub-system. DIGITAL AUDIO 22/25 To Microprocessor EPROM (64Kx8) Control Bus TDA7502 TDA7535 D99AU1036 TDA7502 POWER AMPLIFIER ...

  • Page 23

    ... TDA7502 8 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

  • Page 24

    ... Revision history Date January 2004 September 2004 March 2005 24-Nov-2006 24/25 Revision Description of changes 8 First Issue in EDOCS dms. Changed the style-sheet look. 9 Cancelled the “Package Marking” information. 10 Changed SPI interface description and Figure 4. 11 Package changed, layout changes, text modifications. TDA7502 ...

  • Page 25

    ... TDA7502 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...