IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TAS5508A
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2.1.3 Terminal Descriptions
TERMINAL
(1)
TYPE
TOLERANT
NAME
NO.
AVDD_PLL
9
P
AVSS
5, 6
P
AVSS_PLL
8
P
BKND_ERR
37
DI
DVDD
15, 36
P
DVDD_PWM
54
P
DVSS
16, 34,
P
35, 38
DVSS_PWM
53
P
HP_SEL
12
DI
LRCLK
26
DI
MCLK
63
DI
MUTE
14
DI
OSC_CAP
18
AO
PDN
13
DI
PLL_FLT_RET
2
AO
PLL_FLTM
3
AO
PLL_FLTP
4
AI
PSVC
32
O
PWM_HPML
59
DO
PWM_HPMR
61
DO
PWM_HPPL
60
DO
PWM_HPPR
62
DO
PWM_M_1
40
DO
PWM_M_2
42
DO
PWM_M_3
44
DO
PWM_M_4
46
DO
PWM_M_5
55
DO
PWM_M_6
57
DO
PWM_M_7
49
DO
PWM_M_8
51
DO
PWM_P_1
41
DO
PWM_P_2
43
DO
PWM_P_3
45
DO
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive
inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 200 mA, while maintaining a logic-1 drive level.
16
Description
5-V
(2)
TERMINATION
3.3-V analog power supply for PLL. This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter,
this terminal should be bypassed to AVSS_PLL with a 0.1- F low-ESR
capacitor.
Analog ground
Analog ground for PLL. This terminal should reference the same ground as
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must
be minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground-distribution techniques to achieve a quiet ground reference
at this terminal.
Pullup
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to any system parameters, with
all H-bridge drive signals going to a hard-mute (M) state.
3.3-V digital power supply
3.3-V digital power supply for PWM
Digital ground
Digital ground for PWM
5 V
Pullup
Headphone in/out selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
5 V
Serial-audio data left/right clock (sampling-rate clock)
5 V
Pulldown
MCLK is a 3.3-V master clock input. The input frequency of this clock can range
from 4 MHz to 50 MHz.
5 V
Pullup
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
Oscillator capacitor
5 V
Pullup
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The internal parameters are preserved through
a power-down cycle, as long as RESET is not active. The duration for system
recovery from power down is 100 ms.
PLL external filter return
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
Power-supply volume control PWM output
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 5 output (differential –)
PWM 6 output (differential –)
PWM 7 (lineout L) output (differential –)
PWM 8 (lineout R) output (differential –)
PWM 1 output (differential +)
PWM 2 output (differential +)
PWM 3 output (differential +)
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DESCRIPTION
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