IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TERMINAL
(1)
TYPE
TOLERANT
NAME
NO.
PWM_P_4
47
DO
PWM_P_5
56
DO
PWM_P_6
58
DO
PWM_P_7
50
DO
PWM_P_8
52
DO
RESERVED
21, 22,
23, 64
RESET
11
DI
SCL
25
DI
SCLK
27
DI
SDA
24
DIO
SDIN1
31
DI
SDIN2
30
DI
SDIN3
29
DI
SDIN4
28
DI
VALID
39
DO
VBGAP
10
P
VR_DIG
33
P
VR_DPLL
17
P
VR_PWM
48
P
VRA_PLL
1
P
VRD_PLL
7
P
XTL_IN
20
AI
XTL_OUT
19
AO
(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
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5-V
(2)
TERMINATION
PWM 4 output (differential +)
PWM 5 output (differential +)
PWM 6 output (differential +)
PWM 7 (lineout L) output (differential +)
PWM 8 (lineout R) output (differential +)
Connect to digital ground
5 V
Pullup
System reset input, active-low. A system reset is generated by applying a logic
low to this terminal. RESET is an asynchronous control signal that restores the
TAS5508A to its default conditions, sets the valid output low, and places the
PWM in the hard mute (M) state. Master volume is immediately set to full
attenuation. On the release of RESET, if PDN is high, the system performs a 4-
to 5-ms device initialization and sets the volume at mute.
5 V
2
I
C serial-control clock input/output
5 V
Serial-audio data clock (shift clock) input
5 V
2
I
C serial-control data-interface input/output
5 V
Pulldown
Serial-audio data input 1 is one of the serial-data input ports. SDIN1 supports
four discrete (stereo) data formats and is capable of inputting data at 64 f
5 V
Pulldown
Serial-audio data input 2 is one of the serial-data input ports. SDIN2 supports
four discrete (stereo) data formats and is capable of inputting data at 64 f
5 V
Pulldown
Serial-audio data input 3 is one of the serial-data input ports. SDIN3 supports
four discrete (stereo) data formats and is capable of inputting data at 64 f
5 V
Pulldown
Serial-audio data input 4 is one of the serial-data input ports. SDIN4 supports
four discrete (stereo) data formats and is capable of inputting data at 64 f
Output indicating validity of PWM outputs, active-high
Band-gap voltage reference. A pinout of the internally regulated 1.2-V reference.
Typically has a 1-nF low-ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
Voltage reference for 1.8-V digital core supply. A pinout of the internally
regulated 1.8-V power used by digital core logic. A 4.7- F low-ESR capacitor
should be connected between this terminal and DVSS. This terminal must not
be used to power external devices.
Voltage reference for 1.8-V digital PLL supply. A pinout of the internally
regulated 1.8-V power used by digital PLL logic. A 0.1- F low-ESR capacitor
should be connected between this terminal and DVSS_CORE. This terminal
must not be used to power external devices.
Voltage reference for 1.8-V digital PWM core supply. A pinout of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1- F low-ESR
(3)
capacitor
should be connected between this terminal and DVSS_PWM. This
terminal must not be used to power external devices.
Voltage reference for 1.8-V PLL analog supply. A pinout of the internally
regulated 1.8-V power used by PLL logic. A 0.1- F low-ESR capacitor
be connected between this terminal and AVSS_PLL. This terminal must not be
used to power external devices.
Voltage reference for 1.8-V PLL digital supply. A pinout of the internally
regulated 1.8-V power used by PLL logic. A 0.1- F low-ESR capacitor
be connected between this terminal and AVSS_PLL. This terminal must not be
used to power external devices.
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5508A via use of an external
fundamental-mode crystal. XTL_IN is the 1.8-V input port for the oscillator
circuit. A 13.5-MHz crystal (HCM49) is recommended.
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5508A via use of an external
fundamental-mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. A
13.5-MHz crystal (HCM49) is recommended.
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
DESCRIPTION
Description
TAS5508A
.
S
.
S
.
S
.
S
(3)
(3)
(3)
should
(3)
should
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