IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508A accepts 16-, 20-, or 24-bit serial
data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I
input using a 64-f
SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 f
S
of 50 MHz. The clock speed and serial data format are I
2
2.2.3 I
C Serial-Control Interface
2
The TAS5508A has an I
system controller. The serial-control interface supports both normal-speed (100 kHz) and high-speed (400
kHz) operations without wait states. Because the TAS5508A has a crystal time base, this interface
operates even when MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP
data-processing registers, the serial control interface also supports multiple-byte (4-byte) write operations.
2
The I
C supports a special mode which permits I
data-write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of 4
bytes of data. This permits the system to incrementally write large register values without blocking other
2
I
C transactions. In order to use this feature, the first block of data is written to the target I
each subsequent block of data is written to a special append register (0xFE) until all the data is written
and a stop bit is sent. An incremental read operation is not supported.
2.2.4 Device Control
The TAS5508A control section provides the control and sequencing for the TAS5508A. The device control
provides both high- and low-level control for the serial control interface, clock and serial data interfaces,
digital audio processor, and pulse-width modulator sections.
2.2.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio-processing functions: soft volume, loudness
compensation, bass and treble processing, dynamic range control, channel filtering, input and output
mixing.
Figure 2-1
shows the TAS5508A DAP architecture.
The DAP accepts 24-bit data from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32-kHz to 96-kHz data and one for 176.4-kHz to 192-kHz
data.
2.2.5.1 TAS5508A Audio-Processing Configurations
The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured
either as eight channels, or as six channels with two channels for separate stereo line outputs.
The 176.4-kHz to 192-kHz configuration supports three channels of signal processing with five channels
passed though (or derived from the three processed channels).
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Table 2-1. Serial Data Formats
RECEIVE SERIAL DATA FORMAT
Right-justified
Right-justified
Right-justified
2
I
S
2
I
S
2
I
S
Left-justified
Left-justified
Left-justified
2
C configurable.
C serial-control slave interface (address 0x36) to receive commands from a
2
C write operations to be broken up into multiple
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
WORD LENGTH
16
20
24
16
20
24
16
20
24
2
S, or right-justified format. Data is
, up to a maximum
S
2
C address, and
Description
TAS5508A
19