IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TAS5508A
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
A_to_ipmix
Left
A
SDIN1
B
Right
B_to_ipmix
C_to_ipmix
Left
C
SDIN2
D
Right
D_to_ipmix
Biquads
in
Series
E_to_ipmix
Left
Input
Mixer
E
SDIN3
F
Right
F_to_ipmix
G_to_ipmix
Left
G
SDIN4
H
Right
H_to_ipmix
Figure 2-3. TAS5508A Detailed Channel Processing
2
2.3.2 I
C Coefficient Number Formats
The architecture of the TAS5508A is contained in ROM resources within the TAS5508A and cannot be
altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I
interface, provide a user with the flexibility to set the TAS5508A to a configuration that achieves
system-level goals.
The firmware is executed in a 48-bit, signed, fixed-point arithmetic machine. The most significant bit of the
48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented
by multiplying a 48-bit, signed data value by a 28-bit, signed gain coefficient. The 76-bit, signed output
product is then truncated to a signed, 48-bit number. Level offset operations are implemented by adding a
48-bit, signed offset coefficient to a 48-bit, signed data value. In most cases, if the addition results in
overflowing the 48-bit, signed number format, saturation logic is used. This means that if the summation
results in a positive number that is greater than 0x7FFF FFFF FFFF (the spaces are used to ease the
reading of the hexadecimal number), the number is set to 0x7FFF FFFF FFFF. If the summation results in
a negative number that is less than 0x8000 0000 0000, the number is set to 0x8000 0000 0000.
2.3.2.1 28-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers have 5 bits to the left of the binary point and 23 bits to the right of the binary point. This is shown
in
Figure
2-4.
24
Description
Master
Volume
Channel Volume
Volume
Bass and Treble
Bypass
Loudness
7
Bass
and
Treble
Pre-
Post-
Volume
Volume
Bass
and
Treble
Inline
DRC
Max
DRC
Bypass
Output
Gain
Output Mixer Sums
Any Two Channels
32-Bit
Trunc
DRC
Inline
1 Other
Channel Output
From 7 Available
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PWM
PWM
Proc
Output
B0016-01
2
C bus