IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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3.2.3
Back-End Error (BKND_ERR)
3.2.3.1 BKND_ERR and VALID
3.2.4
Speaker/Headphone Selector (HP_SEL)
3.2.5
Mute (MUTE)
3.3
Device Configuration Controls
3.3.1
Channel Configuration Registers
3.3.2
Headphone Configuration Registers
3.3.3
Audio System Configurations
3.3.3.1 Using Line Outputs in 6-Channel Configurations
3.3.4
Recovery from Clock Error
3.3.5
Power-Supply Volume-Control Enable
3.3.6
Volume and Mute Update Rate
3.3.7
Modulation Index Limit
3.3.8
Interchannel Delay
3.4
Master Clock and Serial Data Rate Controls
3.4.1
PLL Operation
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3.5
Bank Controls
3.5.1
Manual Bank Selection
3.5.2
Automatic Bank Selection
3.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled
..........................................................................................................
3.5.3
Bank Set
3.5.4
Bank-Switch Timeline
3.5.5
Bank-Switching Example 1
3.5.6
Bank-Switching Example 2
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4
Electrical Specifications
4.1
Absolute Maximum Ratings
4.2
Dissipation Rating Table (High-k Board, 105 C Junction)
4.3
Dynamic Performance at Recommended Operating Conditions at 25 C
4.4
Recommended Operating Conditions
4.5
Electrical Characteristics
4.6
PWM Operation
4.7
Switching Characteristics
4.7.1
Clock Signals
4.7.2
Serial Audio Port
2
4.7.3
I
C Serial Control Port Operation
4.7.4
Reset Timing (RESET)
4.7.5
Power-Down (PDN) Timing
4.7.6
Back-End Error (BKND_ERR)
4.7.7
Mute Timing (MUTE)
4.7.8
Headphone Select (HP_SEL)
4.7.9
Volume Control
4.8
Serial Audio Interface Control and Timing
........................................................................................................
2
4.8.1
I
S Timing
4.8.2
Left-Justified Timing
4.8.3
Right-Justified Timing
2
5
I
C Serial-Control Interface (Slave Address 0x36)
2
5.1
General I
C Operation
5.2
Single- and Multiple-Byte Transfers
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5.3
Single-Byte Write
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5.4
Multiple-Byte Write
5.5
Incremental Multiple-Byte Write
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5.6
Single-Byte Read
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8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
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Contents
TAS5508A
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