IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Page 43/105

Download datasheet (2Mb)Embed
PrevNext
www.ti.com
3
TAS5508A Controls and Status
The TAS5508A provides control and status information from both the I
This section describes some of these controls and status functions. The I
register descriptions are contained in
2
3.1
I
C Status Registers
The TAS5508A has two status registers that provide general device information. These are the general
status register 0 (0x01) and the error status register (0x02).
3.1.1 General Status Register (0x01)
Device identification code
Clip indicator – The TAS5508A has a clipping indicator. Writing to the register clears the indicator.
Bank switching is busy.
3.1.2 Error Status Register (0x02)
No internal errors (the valid signal is high)
A clock error has occurred – These are sticky bits that are cleared by writing to the register.
– LRCLK error – when the number of MCLKs per LRCLK is incorrect
– SCLK error – when the number of SCLKS per LRCLK is incorrect
– Frame slip – when the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
– PLL phase-lock error
This error status register is normally used for system development only.
3.2
TAS5508A Pin Controls
The TAS5508A provide a number of terminal controls to manage the device operation. These controls are:
RESET
PDN
BKND_ERR
HP_SEL
MUTE
3.2.1 Reset (RESET)
The TAS5508A is placed in the reset mode either by the power-up reset circuitry when power is applied,
or by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5508A to the hard mute state (M). Master
volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset
without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During
2
reset, all I
C and serial data bus operations are ignored.
Table 3-1
shows the device output signals while RESET is active.
SIGNAL
Valid
PWM P-outputs
PWM M-outputs
SDA
Submit Documentation Feedback
8-Channel Digital Audio PWM Processor
Section 6
and
Section
7.
Table 3-1. Device Outputs During Reset
SIGNAL STATE
Low (M-state)
Low (M-state)
Signal input (not driven)
TAS5508A
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2
C registers and device pins.
2
C summary and detailed
Low
TAS5508A Controls and Status
43