IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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3.2.5 Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS5508A has both master and individual channel mute commands. A terminal
is also provided for the master mute. The active-low master mute I
logically ORed together. If either is set to low, a mute on all channels is performed. The master mute
command operates on all channels regardless of whether the system is in the 6- or 8-channel
configuration.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master mute terminal is used to support a variety of other operations in the TAS5508A, such as
setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A
mute command by the master mute terminal, individual I
bank-switch mute sequence, or automute overrides an unmute command or a volume command. While a
mute is active, the commanded channels are placed in a mute state. When a channel is unmuted, it goes
to the last commanded volume setting that has been received for that channel.
3.3
Device Configuration Controls
The TAS5508A provides a number of system configuration controls that are set at initialization and
following a reset.
Channel configuration
Headphone configuration
Audio system configurations
Recovery from clock error
Power-supply volume-control enable
Volume and mute update rate
Modulation index limit
Interchannel delay
Master clock and data rate controls
Bank controls
3.3.1 Channel Configuration Registers
For the TAS5508A to have full control of the power stages, registers 0x05 to 0x0C must be programmed
to reflect the proper power stage and how each one should be controlled. There are eight channel
configuration registers, one for each channel. For information on using BKND_ERR and VALID, see
Section
3.2.3.1.
The primary reason for using these registers is that different power stages require different handling
during start-up, mute/unmute, shutdown, and error recovery. The TAS5508A must select the sequence
that gives the best click and pop performance and ensures that the bootstrap capacitor is charged
correctly during start-up. This sequence depends on which power stage is present at the TAS5508A
output.
Table 3-5. Description of the Channel Configuration Registers (0x05 to 0x0C)
BIT
D7
Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this
channel is to follow the error recovery sequence or to continue with no interruption.
D6
Determines if the power stage needs the TAS5508A VALID pin to go low to reset the power stage. Some power stages can be
reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
D5
Determines if the power stage needs the TAS5508A VALID pin to go low to mute the power stage. Some power stages can be
muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
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8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2
C register and the MUTE terminal are
2
C mute, the AM interference mute sequence, the
DESCRIPTION
TAS5508A Controls and Status
TAS5508A
47