IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TAS5508A
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
NUMBER OF STEPS
1024
2048
3.3.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation
is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
For negative signals, the PWM modulations fall below 50% toward 0%.
However, the maximum possible modulation does have a limit. During the offtime period, the power stage
connected to the TAS5508A output needs to get ready for the next ontime period. The maximum possible
modulation is then set by the power stage requirements. All Texas Instruments power stages need
maximum modulation to be 97.7%. This is also the default setting of the TAS5508A. Default settings can
be changed in the modulation index register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
3.3.8 Interchannel Delay
An 8-bit value can be programmed into each of the eight PWM interchannel delay registers to add a delay
per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock,
DCLK. The default values are shown in
2
I
C SUBADDRESS
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
This delay is generated in the PWM and can be changed at any time through the serial-control interface
2
I
C registers 0x1B–0x22. The absolute offset for channel 1 is set in I
If used correctly, setting the PWM channel delay can optimize the performance of a
PurePath Digital™ amplifier system. The setting is based on both the type of back-end
power device that is used and the layout. These values are set during initialization using
2
the I
C serial interface. Unless otherwise noted, use the default values given in
3.4
Master Clock and Serial Data Rate Controls
The TAS5508A functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5508A to detect MCLK and the data rate automatically.
The MCLK frequency can be 64
50
TAS5508A Controls and Status
Table 3-8. Volume Ramp Rates in ms (continued)
SAMPLE RATE (kHz)
44.1, 88.2, 176.4
92.88 ms
185.76 ms
Table
3-9.
Table 3-9. Interchannel Delay Default Values
CHANNEL
INTERCHANNEL DELAY DEFAULT (DCLK PERIODS)
1
2
3
4
5
6
7
8
NOTE
f
, 128
f
, 196
f
, 256
S
S
S
32, 48, 96, 192
85.33 ms
170.67 ms
–24
0
–16
16
–24
8
–8
24
2
C subaddress 0x23.
Table
3-9.
f
, 384
f
, 512
f
, or 768
f
.
S
S
S
S
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