IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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The TAS5508A operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, the phase relationship of these signals has no constraint. The TAS5508A accepts a 64
SCLK rate and a 1
f
LRCLK.
S
If the phase of SCLK or LRCLK drifts more than 10 MCLK cycles since the last reset, the TAS5508A
senses a clock error and resynchronizes the clock timing.
The clock and serial data interface have several control parameters:
MCLK ratio (64 f
, 128 f
S
Data rate (32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz) – I
AM mode enable/disable – I
During AM interference avoidance, the clock control circuitry uses three other configuration inputs:
Tuned AM frequency (for AM interference avoidance) (550 kHz to 1750 kHz) – I
Frequency set select (1–4) – I
2
Sample rate – I
C parameter or auto-detected
3.4.1 PLL Operation
The TAS5508A uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital
PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL
provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz
crystal provides the input reference clock for the DPLL. The crystal provides a time base to support a
number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions.
The crystal time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5508A can receive and store I
3.5
Bank Controls
The TAS5508A permits the user to specify and assign sample-rate-dependent parameters for biquad,
loudness, DRC, and tone in one of three banks that can be manually selected or selected automatically
based on the data sampling rate. Each bank can be enabled for one or more specific sample rates via I
bank control register 0x40. Each bank set holds the following values:
Coefficients for seven biquads (7
0x51–0x88)
Coefficients for one loudness biquad (register 0x95)
DRC1 energy and (1 – energy) values (register 0x98)
DRC1 attack, (1 – attack), decay, (1 – decay) values (register 0x9C)
DRC2 energy and (1 – energy) values (register 0x9D)
DRC2 attack, (1 – attack), decay, (1 – decay) values (register 0xA1)
Five bass filter-set selections (register 0xDA)
Five treble filter-set selections (register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is
used, bank 2 and bank 3 must be programmed on power up, because the default values are all zeroes. If
bank switching is used and bank 2 and bank 3 are not programmed correctly, then the output of the
TAS5508A could be muted when switching to those banks.
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, 196 f
, 256 f
, 384 f
, 512 f
, or 768 f
S
S
S
S
S
2
C parameter
2
C parameter
2
C parameter
5 = 35 coefficients) for each of the eight channels (registers
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2
) – I
C parameter
S
2
C parameter
2
C commands and provide status.
TAS5508A Controls and Status
TAS5508A
f
S
2
C
51