IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TAS5508A
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
During multiple-byte write operations, the TAS5508A compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5508A expects to receive five 32-bit words. If fewer than five 32-bit data
words have been received when a stop command (or another start command) is received, the data
received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5508A
expects to receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I
TAS5508A also supports sequential I
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
2
TAS5508A. For I
C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As is true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data
is discarded.
5.3
Single-Byte Write
As shown in
Figure
5-2, a single-byte, data-write transfer begins with the master device transmitting a start
condition followed by the I
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
2
I
C device address and the read/write bit, the TAS5508A device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5508A internal memory address
being accessed. After receiving the address byte, the TAS5508A again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5508A again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte, data-write transfer.
Start
Condition
A0 R/W ACK A7
A6
A5
A4
A3
A2
A1
2
I C Device Address and
Read/Write Bit
5.4
Multiple-Byte Write
A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5508A, as shown in
data byte, the TAS5508A responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
2
66
I
C Serial-Control Interface (Slave Address 0x36)
2
C addressing. For write transactions, if a subaddress is issued
2
C device address and the read/write bit. The read/write bit determines the
Acknowledge
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Subaddress
Figure 5-2. Single-Byte Write Transfer
Acknowledge
A6
A5
A4
A3
A1
A0 ACK D7
D0
Subaddress
First Data Byte
Figure 5-3. Multiple-Byte Write Transfer
2
C addressing. The
Acknowledge
D6
D5
D4
D3
D2
D1
D0 ACK
Data Byte
Figure
5-3. After receiving each
Acknowledge
Acknowledge
Acknowledge
ACK
D7
D0
ACK
D7
D0 ACK
Other Data Bytes
Last Data Byte
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2
C write
Stop
Condition
T0036-01
Stop
Condition
T0036-02