IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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5.5
Incremental Multiple-Byte Write
2
The I
C supports a special mode which permits I
write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of
four bytes of data. This permits the system to write large register values incrementally without blocking
2
other I
C transactions.
This feature is enabled by the append subaddress function in the TAS5508A. This function enables the
TAS5508A to append four bytes of data to a register that was opened by a previous I
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5508A starts processing the data.
The procedure to perform an incremental multibyte-write operation is as follows:
2
1. Start a normal I
C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing four-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the
remaining number of bytes in sequential order to complete the register write operation. Each of these
append operations is composed of the device address, write bit, append subaddress (0xFE), and four
bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
a. If a new subaddress is written to the TAS5508A before the correct number of bytes are written.
b. If more or fewer than four bytes are data written at the beginning or during any of the append
operations.
c. If a read bit is sent.
5.6
Single-Byte Read
As shown in
Figure
5-4, a single-byte, data-read transfer begins with the master device transmitting a start
2
condition followed by the I
and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes
of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the
TAS5508A address and the read/write bit, the TAS5508A responds with an acknowledge bit. In addition,
after sending the internal memory address byte or bytes, the master device transmits another start
condition followed by the TAS5508A address and the read/write bit again. This time the read/write bit is a
1, indicating a read transfer. After receiving the TAS5508A and the read/write bit the TAS5508A again
responds with an acknowledge bit. Next, the TAS5508A transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not acknowledge followed by a
stop condition to complete the single-byte, data-read transfer.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Submit Documentation Feedback
2
C write operations to be broken up into multiple data
C device address and the read/write bit. For the data-read transfer, both a write
Repeat Start
Condition
Acknowledge
A6
A5
A4
A0 ACK
A6
A5
2
Subaddress
I C Device Address and
Read/Write Bit
Figure 5-4. Single-Byte Read Transfer
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2
C register write
Not
Acknowledge
Acknowledge
A1
A0
R/W
ACK
D7
D6
D1
D0 ACK
Data Byte
2
I
C Serial-Control Interface (Slave Address 0x36)
TAS5508A
Stop
Condition
T0036-03
67