IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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2
6
Serial-Control I
C Register Summary
The TAS5508A slave address is 0x36. See Serial-Control Interface Register Definitions,
complete bit definitions.
Note that u indicates unused bits.
2
TOTAL
I
C
REGISTER FIELDS
BYTES
SUBADDRESS
0x00
1
Clock control register
0x01
1
General status register
0x02
1
Error status register
0x03
1
System control register 1
0x04
1
System control register 2
Channel configuration
0x05–0x0C
1/reg.
control registers
Headphone configuration
0x0D
1
control register
0x0E
1
Serial data interface control
register
0x0F
1
Soft mute register
0x10–0x13
0x14
1
Automute control register
0x15
1
Automute PWM threshold
and back-end reset period
register
0x16
1
Modulation index limit
register
0x17–0x1A
0x1B–0x22
1/reg.
Interchannel delay registers
0x23
1
Channel offset register
0x24–0x3F
0x40
4
Bank-switching command
register
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8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
DESCRIPTION OF CONTENTS
Set data rate and MCLK frequency
1. f
= 48 kHz
S
2. MCLK = 256 f
Clip indicator and ID code for the
0x01
TAS5508A
PLL, SCLK, LRCLK, and frame slip
No errors
errors
1. PWM high pass disabled
PWM high pass, clock set, unmute
2. Auto clock set
select, PSVC select
3. Hard unmute on clock error recovery
4. PSVC Hi-Z disabled
1. Automute time-out disabled
2. Post-DAP detection automute enabled
Automute and de-emphasis control
3. 8-Ch device input detection automute enabled
4. Unmute threshold 6 dB over input
5. No de-emphasis
1. Enable back-end reset.
2. Valid low for reset
3. Valid low for mute
Configure channels 1, 2, 3, 4, 5, 6, 7,
4. Normal BEPolarity
and 8
5. Do not remap the output for the TAS5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
1. Disable back-end reset sequence.
2. Valid does not have to be low for reset.
3. Valid does not have to be low for mute.
Configure headphone output
4. Normal BEPolarity
5. Do not remap output to comply with 5182.
6. Do not go low-low in mute.
7. Do not remap Hi-Z state to low-low state.
Set serial data interface to
24-bit I
2
right-justified, I
S, or left-justified.
Soft mute for channels 1, 2, 3, 4, 5, 6,
Unmute all channels.
7, and 8
Reserved
Set automute delay and threshold.
1. Set automute delay = 5 ms.
2. Set automute threshold less than bit 8.
Set PWM automute threshold; set
1. Set the PWM threshold the same as the
back-end reset period.
TAS5508A input threshold.
2. Set back-end reset period = 5 ms.
Set modulation index.
97.7%
Reserved
Channel 1 delay = –23 DCLK periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = –16 DCLK periods
Channel 4 delay = 16 DCLK periods
Set interchannel delay.
Channel 5 delay = –24 DCLK periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = –8 DCLK periods
Channel 8 delay = 24 DCLK periods
Absolute delay offset for channel 1
Minimum absolute default = 0 DCLK periods
(0–255)
Reserved
Set up DAP coefficients bank
Manual selection – bank 1
switching for banks 1, 2, and 3
Serial-Control I
TAS5508A
Section 7
for
DEFAULT STATE
= 12.288 MHz
S
2
S
2
69
C Register Summary