IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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TAS5508A
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
2
TOTAL
I
C
REGISTER FIELDS
BYTES
SUBADDRESS
Input mixer registers,
0x41–0x48
32/reg.
Ch1–Ch8
0x49
4
ipmix_1_to_ch8
0x4A
4
ipmix_2_to_ch8
0x4B
4
ipmix_7_to_ch2
0x4C
4
Ch7_bp_bq2
0x4D
4
Ch7_bq2
0x4E
4
ipmix_8_to_ch12
0x4F
4
Ch8_bp_bq2
0x50
4
Ch8_bq2
0x51–0x88
20/reg.
Biquad filter register
0x89–0x90
8
Bass and treble bypass
register, Ch1–Ch8
0x91
4
Loudness Log2 LG
0x92
8
Loudness Log2 LO
0x93
4
Loudness G
0x94
8
Loudness O
0x95
20
Loudness biquad
0x96
4
DRC1 control Ch1–Ch7
0x97
4
DRC2 control register, Ch8
Ch1–Ch7, DRC1 energy
0x98
8
Ch1–Ch7, DRC1 (1 –
energy)
Ch1–Ch7 DRC1 threshold
T1
0x99
16
Ch1–Ch7 DRC1 threshold
T2
Ch1–Ch7 , DRC1 slope k0
0x9A
12
Ch1–Ch7, DRC1 slope k1
Ch1–Ch7 DRC1 slope k2
Ch1–Ch7 DRC1 offset 1
0x9B
16
Ch1–Ch7 DRC1 offset 2
Ch1–Ch7 DRC1 attack
Ch1–Ch7 DRC1 (1 – attack)
0x9C
16
Ch1–Ch7 DRC1 decay
Ch1–Ch7 DRC1 (1 – decay)
Ch8 DRC2 energy
0x9D
8
Ch8 DRC2 (1 – energy)
Ch8 DRC2 threshold T1
0x9E
16
Ch8 DRC2 threshold T2
2
70
Serial-Control I
C Register Summary
DESCRIPTION OF CONTENTS
SDIN1 – left to input mixer 1
SDIN1 – right to input mixer 2
SDIN2 – left to input mixer 3
SDIN2 – right to input mixer 4
8 8 input crossbar mixer setup
SDIN3 – left to input mixer 5
SDIN3 – right to input mixer 6
SDIN4 – left to input mixer 7
SDIN4 – right to input mixer 8
Input mixer 1 to Ch8 mixer coefficient
0.0
Input mixer 1 to Ch8 mixer coefficient
0.0
Input mixer 7 to Ch2 mixer coefficient
0.0
Bypass Ch7 biquad 2 coefficient
0.0
Ch7 biquad 2 coefficient
1.0
Ch8 biquad 2 output to Ch1 mixer and
0.0
Ch2 mixer coefficient
Bypass Ch8 biquad 2 coefficient 0
0.0
Ch8 biquad 2 coefficient
1.0
Ch1–Ch8 biquad filter coefficients
All biquads = All pass for all channels
Bypass bass and treble for Ch1–Ch8
Bass and treble bypassed for all channels
Loudness Log2 LG
0.5
Loudness Log2 LO
0.0
Loudness G
0.0
Loudness O
0.0
Loudness biquad coefficient b0
0x00, 0x00, 0xD5, 0x13
Loudness biquad coefficient b1
0x00, 0x00, 0x00, 0x00
Loudness biquad coefficient b2
0x0F, 0xFF, 0x2A, 0xED
Loudness biquad coefficient a0
0x00, 0xFE, 0x50, 0x45
Loudness biquad coefficient a1
0x0F, 0x81, 0xAA, 0x27
DRC1 control Ch1–Ch7
DRC1 disabled in Ch1–Ch7
DRC2 control Ch8
DRC2 disabled in Ch8
DRC1 energy
0.0041579
DRC1 (1 – energy)
0.9958421
DRC1 threshold (T1) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC1 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
DRC1 threshold (T2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC1 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
DRC1 slope (k0)
0x0F, 0xC0, 0x00, 0x00
DRC1 slope (k1)
0x0F, 0xC0, 0x00, 0x00
DRC1 slope (k2)
0x0F, 0x90, 0x00, 0x00
DRC1 offset 1 (O1) – upper 2 bytes
0x00, 0x00, 0xFF, 0xFF
DRC1 offset 1 (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
DRC1 offset 2 (O2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC1 offset 2 (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
DRC1 attack
0x00, 0x00, 0x88, 0x3F
DRC1 (1 – attack)
0x00, 0x7F, 0x77, 0xC0
DRC1 decay
0x00, 0x00, 0x00, 0xAE
DRC1 (1 – decay)
0x00, 0x7F, 0xFF, 0x51
DRC2 energy
0x00, 0x00, 0x88, 0x3F
DRC2 (1 – energy)
0x00, 0x7F, 0x77, 0xC0
DRC2 threshold (T1) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC2 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
DRC2 threshold (T2) – upper 2 bytes
0x00, 0x00, 0x00, 0x00
DRC2 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
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DEFAULT STATE
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