IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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Table 7-19. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) (continued)
DESCRIPTION
b
coefficient
u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0]
1
b
coefficient
u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0]
2
a
coefficient
u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0]
1
a
coefficient
u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0]
2
7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
and 0x90, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23)
format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits
not used.
Table 7-20. Channel 1–8 Bass and Treble Bypass Register Format
REGISTER
TOTAL
NAME
BYTES
Channel bass and
u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0]
treble bypass
8
Channel bass and
u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0]
treble inline
7.20 Loudness Registers (0x91–0x95)
2
I
C SUB-
TOTAL
REGISTER NAME
ADDRESS BYTES
0x91
4
Loudness Log2 gain (LG)
Loudness Log2 offset (LO)
0x92
8
Loudness Log2 LO
0x93
4
Loudness gain (G)
Loudness offset upper
16 bits (O)
0x94
8
Loudness O offset lower 32
bits (O)
Loudness biquad (b
Loudness biquad (b
0x95
20
Loudness biquad (b
Loudness biquad (a
Loudness biquad (a
7.21 DRC1 Control Registers, Channels 1–7 (0x96)
Bits D31–D14 are Don't Care.
Table 7-22. Channel 1–7 DCR1 Control Register Format
D31
D30
D29
D28
D27
D23
D22
D21
D20
D19
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REGISTER FIELD CONTENTS
CONTENTS
Table 7-21. Loudness Register Format
DESCRIPTION OF CONTENTS
u[31:28], LG[27:24], LG[23:16], LG[15:8], LG[7:0]
u[31:24], u[23:16], LO[15:8], LO[7:0]
LO[31:24], LO[23:16], LO[15:8], LO[7:0]
u[31:28], G[27:24], G[23:16], G[15:8], G[7:0]
u[31:24], u[23:16], O[15:8], O[7:0]
O[31:24], O[23:16], O[15:8], O[7:0]
)
u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0]
0
)
u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0]
1
)
u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0]
2
)
u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0]
1
)
u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0]
2
D26
D25
D24
Unused bits
D18
D17
D16
Unused bits
8-Channel Digital Audio PWM Processor
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
DEFAULT GAIN COEFFICIENT VALUES
DECIMAL
HEX
0.0
0x00, 0x00, 0x00, 0x00
0.0
0x00, 0x00, 0x00, 0x00
0.0
0x00, 0x00, 0x00, 0x00
0.0
0x00, 0x00, 0x00, 0x00
INITIALIZATION VALUE
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
DEFAULT STATE
0xFF, 0xC0, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
FUNCTION
FUNCTION
Serial-Control Interface Register Definitions
TAS5508A
85