IC DGTL AUDIO PWM PROC 64-TQFP

TAS5508APAG

Manufacturer Part NumberTAS5508APAG
DescriptionIC DGTL AUDIO PWM PROC 64-TQFP
ManufacturerTexas Instruments
TypePWM Processor
TAS5508APAG datasheet
 


Specifications of TAS5508APAG

ApplicationsDVDMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPFor Use WithTAS5342DDV6EVM - TAS5342DDV6EVMTAS5508-5142K7EVM - EVAL MODULE FOR TAS5508B/TAS5142TAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5508-5121K8EVM - EVAL MODULE FOR TAS5508B/TAS5121
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names296-17475
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7.22 DRC2 Control Register, Channel 8 (0x97)
Table 7-23. Channel-8 DRC2 Control Register Format
D31–D2
D1
D0
0
0
0
0
Channel 8 (node r): no DRC
0
0
0
1
Channel 8 (node r): pre-volume DRC
0
0
1
0
Channel 8 (node r): post-volume DRC
0
0
1
1
Channel 8 (node r): no DRC
7.23 DRC1 Data Registers (0x98–0x9C)
DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7.
2
I
C
TOTAL
REGISTER NAME
SUB-
BYTES
ADDRESS
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
energy
0x98
8
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
(1 – energy)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
threshold upper 16 bits (T1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
threshold lower 32 bits (T1)
0x99
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
threshold upper 16 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
threshold lower 32 bits (T2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
slope (k0)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
0x9A
12
slope (k1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
slope (k2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
offset 1 upper 16 bits (O1)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
offset 1 lower 32 bits (O1)
0x9B
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
offset 2 upper 16 bits (O2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
offset 2 lower 32 bits (O2)
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
attack
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
(1 – attack)
0x9C
16
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
decay
Channel 1, 2, 3, 4, 5, 6, and 7 DRC1
(1 – decay)
7.24 DRC2 Data Registers (0x9D–0xA1)
DRC2 applies to channel 8.
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8-Channel Digital Audio PWM Processor
FUNCTION
Table 7-24. DRC1 Data Register Format
DESCRIPTION OF CONTENTS
u[31:28], E[27:24], E[23:16], E[15:8], E[7:0]
u[31:28], 1–E[27:24], 1–E[23:16], 1–E[15:8], 1–E[7:0]
u[31:24], u[23:16], T1[15:8], T1[7:0]
T1[31:24], T1[23:16], T1[15:8], T1[7:0]
u[31:24], u[23:16], T2[15:8], T2[7:0]
T2[31:24], T2[23:16], T2[15:8], T2[7:0]
u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0]
u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0]
u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0]
u[31:24], u[23:16], O1[15:8], O1[7:0]
O1[31:24], O1[23:16], O1[15:8], O1[7:0]
u[31:24], u[23:16], O2[15:8], O2[7:0]
O2[31:24], O2[23:16], O2[15:8], O2[7:0]
u[31:28], A[27:24], A[23:16], A[15:8], A[7:0]
u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0]
u[31:28], D[27:24], D[23:16], D[15:8], D[7:0]
u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 1–D[7:0]
TAS5508A
SLES119A – FEBRUARY 2004 – REVISED JULY 2009
DEFAULT STATE
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
Serial-Control Interface Register Definitions
87