LPC1343FBD48 NXP Semiconductors, LPC1343FBD48 Datasheet
LPC1343FBD48
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LPC1343FBD48 Summary of contents
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LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller flash and 8 kB SRAM; USB device Rev. 4 — 20 June 2011 1. General description The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of ...
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... NXP Semiconductors Serial interfaces: USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43 only). UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support. SSP controller with FIFO and multi-protocol capabilities. Additional SSP controller on LPC1313FBD48/01. ...
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... LPC1311FHN33 HVQFN33 LPC1311FHN33/01 HVQFN33 LPC1313FHN33 HVQFN33 LPC1313FHN33/01 HVQFN33 LPC1313FBD48 LQFP48 LPC1313FBD48/01 LQFP48 LPC1342FHN33 HVQFN33 LPC1342FBD48 LQFP48 LPC1343FHN33 HVQFN33 LPC1343FBD48 LQFP48 4.1 Ordering options Table 2. Ordering options for LPC1311/13/42/43 Type number Flash LPC1311FHN33 8 kB LPC1311FHN33/ LPC1313FHN33 32 kB LPC1313FHN33/ LPC1313FBD48 32 kB LPC1313FBD48/01 ...
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... NXP Semiconductors Table 2. Ordering options for LPC1311/13/42/43 Type number Flash LPC1342FHN33 16 kB LPC1342FBD48 16 kB LPC1343FHN33 32 kB LPC1343FBD48 32 kB LPC1311_13_42_43 Product data sheet …continued Total USB Power UART SRAM profiles RS-485 4 kB Device Device Device Device ...
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... NXP Semiconductors 5. Block diagram I-code bus HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (2) DTR, DSR , CTS, (2) (2) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 (1) LPC1342/43 only. (2) LQFP48 package only. (3) On LPC1313FBD48/01 only. ...
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... PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. LPC1342/43 LQFP48 package LPC1311_13_42_43 Product data sheet PIO2_6 XTALIN 6 LPC1342FBD48 7 XTALOUT LPC1343FBD48 PIO2_7 11 12 PIO2_8 All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller 36 PIO3_0 35 R/PIO1_2/AD3/CT32B1_MAT1 ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 3. LPC1342/43 HVQFN33 package LPC1311_13_42_43 Product data sheet terminal 1 index area PIO2_0/DTR 1 RESET/PIO0_0 XTALIN LPC1342FHN33 5 XTALOUT LPC1343FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 ...
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... NXP Semiconductors PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 (1) SSP1 or UART function on LPC1313FBD48/01 only. Fig 4. LPC1313 LQFP48 package LPC1311_13_42_43 Product data sheet 1 ( LPC1313FBD48 6 LPC1313FBD48/ All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_2/SSEL0/CT16B0_CAP0 Fig 5. LPC1311_13_42_43 Product data sheet terminal 1 index area PIO2_0/DTR 1 RESET/PIO0_0 2 3 LPC1311FHN33 LPC1311FHN33/01 4 XTALIN LPC1313FHN33 XTALOUT 5 LPC1313FHN33/ PIO1_8/CT16B1_CAP0 7 8 Transparent top view LPC1311/13 HVQFN33 package All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 ...
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... NXP Semiconductors 6.2 Pin description Table 3. LPC1313/42/43 LQFP48 pin description table Symbol Pin Start logic input [2] RESET/PIO0_0 3 yes [3] PIO0_1/CLKOUT/ 4 yes CT32B0_MAT2/ USB_FTOGGLE [3] PIO0_2/SSEL0/ 10 yes CT16B0_CAP0 [3] PIO0_3/USB_VBUS 14 yes [4] PIO0_4/SCL 15 yes [4] PIO0_5/SDA 16 yes [3] PIO0_6/ 22 yes USB_CONNECT/ SCK0 [3] PIO0_7/CTS 23 yes [3] PIO0_8/MISO0/ 27 yes CT16B0_MAT0 LPC1311_13_42_43 Product data sheet ...
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... NXP Semiconductors Table 3. LPC1313/42/43 LQFP48 pin description table Symbol Pin Start logic input [3] PIO0_9/MOSI0/ 28 yes CT16B0_MAT1/ SWO [3] SWCLK/PIO0_10/ 29 yes SCK0/CT16B0_MAT2 [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1/ 34 yes AD2/CT32B1_MAT0 [5] R/PIO1_2/ 35 yes AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/ 39 yes AD4/ CT32B1_MAT2 [5] PIO1_4/AD5/ 40 yes CT32B1_MAT3/ WAKEUP LPC1311_13_42_43 Product data sheet … ...
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... NXP Semiconductors Table 3. LPC1313/42/43 LQFP48 pin description table Symbol Pin Start logic input [3] PIO1_5/RTS/ 45 yes CT32B0_CAP0 [3] PIO1_6/RXD/ 46 yes CT32B0_MAT0 [3] PIO1_7/TXD/ 47 yes CT32B0_MAT1 [3] PIO1_8/CT16B1_CAP0 9 yes [3] PIO1_9/CT16B1_MAT0 17 yes [5] PIO1_10/AD6/ 30 yes CT16B1_MAT1 [5] PIO1_11/AD7 42 yes [3] PIO2_0/DTR/SSEL1 2 yes [3] PIO2_1/DSR/SCK1 13 yes [3] PIO2_2/DCD/MISO1 26 yes [3] PIO2_3/RI/MOSI1 38 yes [3] PIO2_4 ...
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... NXP Semiconductors Table 3. LPC1313/42/43 LQFP48 pin description table Symbol Pin Start logic input [3] PIO2_10 25 yes [3] PIO2_11/SCK0 31 yes [3] PIO3_0/DTR 36 yes [3] PIO3_1/DSR 37 yes [3] PIO3_2/DCD 43 yes [3] PIO3_3/RI 48 yes [3] PIO3_4 18 no [3] PIO3_5 21 no [6] USB_DM 19 no [6] USB_DP [7] XTALIN 6 - [7] XTALOUT [1] Pin state at reset for default function Input ...
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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [2] RESET/PIO0_0 2 yes [3] PIO0_1/CLKOUT/ 3 yes CT32B0_MAT2/ USB_FTOGGLE [3] PIO0_2/SSEL0/ 8 yes CT16B0_CAP0 [3] PIO0_3/ 9 yes USB_VBUS [4] PIO0_4/SCL 10 yes [4] PIO0_5/SDA 11 yes [3] PIO0_6/ 15 yes USB_CONNECT/ SCK0 [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO0/ 17 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 yes CT16B0_MAT1/ ...
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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [3] SWCLK/PIO0_10/ 19 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2/ 23 yes CT32B1_MAT0 [5] R/PIO1_2/AD3/ 24 yes CT32B1_MAT1 [5] SWDIO/PIO1_3/ 25 yes AD4/ CT32B1_MAT2 [5] PIO1_4/AD5/ 26 yes CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS/ 30 yes CT32B0_CAP0 [3] PIO1_6/RXD/ ...
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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [3] PIO1_7/TXD/ 32 yes CT32B0_MAT1 [3] PIO1_8/ 7 yes CT16B1_CAP0 [3] PIO1_9/ 12 yes CT16B1_MAT0 [5] PIO1_10/AD6/ 20 yes CT16B1_MAT1 [5] PIO1_11/AD7 27 yes [3] PIO2_0/DTR 1 yes [3] PIO3_2 28 yes [3] PIO3_4 13 no [3] PIO3_5 14 no [6] USB_DM 13 no [6] USB_DP ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices ...
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... NXP Semiconductors LPC1311/13/42/ private peripheral bus AHB peripherals APB peripherals boot ROM 8 kB SRAM (LPC1313/1343) I-code/D-code memory space 4 kB SRAM (LPC1311/1342 on-chip flash (LPC1313/43 on-chip flash (LPC1342 on-chip flash (LPC1311 Fig 6. LPC1311/13/42/43 memory map 7 ...
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... NXP Semiconductors 7.6.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC1311/13/42/43, the NVIC supports vectored interrupts. In addition the individual GPIO inputs are NVIC-vector capable. • 8 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table. ...
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... NXP Semiconductors • On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled • On the LPC1311/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) are pulled block. 7.9 USB interface (LPC1342/43 only) The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals ...
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... NXP Semiconductors 7.10 UART The LPC1311/13/42/43 contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. ...
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... NXP Semiconductors 2 The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... NXP Semiconductors 7.14 General purpose external event counter/timers The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt ...
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... NXP Semiconductors • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. It ...
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... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USBPLLCLKSEL (USB clock select) The USB clock is available on LPC1342/43 only. SSP1 is available on LPC1313FBD48/01 only. Fig 7. LPC1311/13/42/43 clocking generation block diagram 7.18.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU ...
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... NXP Semiconductors Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... NXP Semiconductors 7.18.5 Power control The LPC1311/13/42/43 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...
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... NXP Semiconductors 7.18.5.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the WAKEUP pin. A LOW-going pulse as short wakes up the part from Deep power-down mode. ...
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... NXP Semiconductors There are three levels of Code Read Protection: 1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. ...
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... NXP Semiconductors The vector table may be located anywhere within the bottom Cortex-M3 address space. The vector table must be located on a 256 word boundary. 7.20 Emulation and debugging Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported. LPC1311_13_42_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) LPC1300 series (LPC1311/13/42/43) power consumption I supply current DD LPC1300L series (LPC1311/01, LPC1313/01) power consumption in low-current mode I supply current DD Standard port pins and RESET pin; see ...
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... NXP Semiconductors Table 7. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit ...
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... NXP Semiconductors Table 7. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter I pull-up current C-bus pins (PIO0_4 and PIO0_5); see V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I input leakage current LI Oscillator pins ...
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... NXP Semiconductors [7] For LPC1342/43: USB_DP and USB_DM pulled LOW externally. [8] IRC disabled; system oscillator enabled; system PLL enabled. [9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF. [10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 9.1 BOD static characteristics for LPC1300 series Remark: Applies to parts LPC1311/13/42/43 and all their packages. Table C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx user manual. LPC1311_13_42_43 Product data sheet ...
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... NXP Semiconductors 9.2 BOD static characteristics for LPC1300L series (LPC1311/01 and LPC1313/01) Remark: Applies to parts LPC1311/01 and LPC1313/01 and all packages. Table 10 C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx user manual ...
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... NXP Semiconductors (mA) Fig 9. (mA) Fig 10. Typical supply current versus temperature in Active mode (LPC1311/13/42/43) LPC1311_13_42_43 Product data sheet MHz MHz 36 MHz 9 24 MHz 6 12 MHz 3 2.0 2 C; Active mode entered executing code Conditions: T amb internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; ...
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... NXP Semiconductors (mA) Fig 11. Typical supply current versus temperature in Sleep mode (LPC1311/13/42/43) (μA) Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks LPC1311_13_42_43 Product data sheet 10 72 MHz MHz 6 36 MHz 4 24 MHz 12 MHz 2 0 −40 −15 Conditions 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system DD oscillator and system PLL enabled ...
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... NXP Semiconductors (μA) Fig 13. Typical supply current versus temperature in Deep power-down mode 9.4 Power consumption for LPC1300L series (LPC1311/01 and LPC1313/01) Remark: Applies to parts LPC1311/01 and LPC1313/01 and all their packages. Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual): • ...
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... NXP Semiconductors (mA) Fig 14. Typical supply current versus regulator supply voltage V (mA) Fig 15. Typical supply current versus temperature in Active mode (LPC1311/01 and LPC1311_13_42_43 Product data sheet MHz 12 48 MHz 8 36 MHz 24 MHz 4 12 MHz 0 2.0 2 C; Active mode entered executing code ...
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... NXP Semiconductors (mA) Fig 16. Typical supply current versus temperature in Sleep mode (LPC1311/01 and (μA) Fig 17. Typical supply current versus temperature in Deep-sleep mode (analog blocks LPC1311_13_42_43 Product data sheet 8 72 MHz MHz 4 36 MHz 24 MHz 2 12 MHz 0 ˗40 ˗15 Conditions 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system DD oscillator and system PLL enabled ...
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... NXP Semiconductors (µA) Fig 18. Typical supply current versus temperature in Deep power-down mode 9.5 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...
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... NXP Semiconductors Table 11. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA n/a 12 MHz GPIO - 0.21 IOCONFIG - 0.00 I2C - 0.03 ROM - 0.04 SSP0 - 0.11 SSP1 - 0.11 UART - 0.20 WDT - 0.01 USB - - USB - 1.84 9.6 Electrical pin characteristics V Fig 19. High-drive output: Typical HIGH-level output voltage V LPC1311_13_42_43 Product data sheet ...
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... NXP Semiconductors (mA) Fig 20. I (mA) Fig 21. Typical LOW-level output current I LPC1311_13_42_43 Product data sheet 0.2 Conditions 3 pins PIO0_4 and PIO0_5 C-bus pins (high current sink): Typical LOW-level output current I LOW-level output voltage 0.2 Conditions 3.3 V; standard port pins and PIO0_7. ...
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... NXP Semiconductors V Fig 22. Typical HIGH-level output voltage V (μA) Fig 23. Typical pull-up current I LPC1311_13_42_43 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V ...
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... NXP Semiconductors (μA) Fig 24. Typical pull-down current I LPC1311_13_42_43 Product data sheet ° °C −40 ° Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 12. = 40 C to +85 C. T amb Symbol Parameter wait V I [1] See [2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. Fig 25. Power-up ramp 10.2 Flash memory Table 13. ...
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... NXP Semiconductors 10.3 External clock Table 14. Dynamic characteristic: external clock = 40 C to +85 over specified ranges. amb DD Symbol Parameter f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time ...
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... NXP Semiconductors 10.4 Internal oscillators Table 15. Dynamic characteristics: IRC = 40 C to +85 C; 2.7 V amb Symbol Parameter f internal RC oscillator frequency osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 10.5 I/O pins Table 17. Dynamic characteristics: I/O pins = 40 C to +85 C; 3.0 V amb Symbol Parameter t rise time r t fall time f [1] Applies to standard port pins and RESET pin. 2 10.6 I C-bus Table 18. Dynamic characteristic 40 C to +85 C. [2] T amb Symbol ...
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... NXP Semiconductors could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t [8] The maximum t HD;DAT transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. ...
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... NXP Semiconductors 10.7 SSP0/1 interface Remark: The SSP1 interface is available on the LPC1313FBD48/01 only. Table 19. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 29. SSP master timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 30. SSP slave timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 4 — 20 June 2011 ...
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... NXP Semiconductors 10.8 USB interface (LPC1342/43 only) Table 20. Dynamic characteristics: USB pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions (LPC1342/43 only) LPC134x Fig 32. LPC1342/43 USB interface on a self-powered device LPC134x Fig 33. LPC1342/43 USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors Fig 34. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...
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... NXP Semiconductors Table 21. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 22. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...
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... NXP Semiconductors 11.4 Standard I/O pad configuration Figure 36 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output pin configured as digital input pin configured as analog input Fig 36 ...
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... NXP Semiconductors 11.5 Reset pad configuration Fig 37. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1311/13/42/43 chip. • ...
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... IEC level Input clock: crystal oscillator (12 MHz) maximum peak level IEC level [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. LPC1311_13_42_43 Product data sheet ElectroMagnetic Compatibility (EMC) for part LPC1343FBD48 (TEM-cell method) amb Frequency band System clock = 12 MHz 6 150 kHz - 30 MHz ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 40. Reflow soldering of the LQFP48 package LPC1311_13_42_43 Product data sheet (8× Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 41. Reflow soldering of the HVQFN33 package LPC1311_13_42_43 Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7.95 CU solder land plus solder paste ...
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... NXP Semiconductors 14. Abbreviations Table 24. Acronym A/D ADC AHB AMBA APB BOD EOP ETM FIFO GPIO HID I/O LSB MSC PHY PLL SE0 SPI SSI SSP SoF TCM TTL UART USB LPC1311_13_42_43 Product data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus ...
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... NXP Semiconductors 15. Revision history Table 25. Revision history Document ID Release date LPC1311_13_42_43 v.4 20110620 Modifications: LPC1311_13_42_43 v.3 20100810 LPC1311_13_42_43 v.2 20100506 LPC1311_13_42_43 v.1 20091211 LPC1311_13_42_43 Product data sheet Data sheet status Product data sheet • Parts LPC1311/01 and LPC1313/01 added (LPC1300L series). • Modifications to the data sheet applying to the LPC1311/01 and LPC1313/01 only: – ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC1311_13_42_43 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 17 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 17 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 17 7.3 On-chip flash program memory . . . . . . . . . . . 17 7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Memory map ...
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... NXP Semiconductors 11.4 Standard I/O pad configuration . . . . . . . . . . . . 61 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 62 11.6 ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 62 11.7 ElectroMagnetic Compatibility (EMC Package outline . . . . . . . . . . . . . . . . . . . . . . . . 64 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 69 16 Legal information 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 70 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘ ...