The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part NumberLPC1759FBD80
DescriptionThe LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
ManufacturerNXP Semiconductors
LPC1759FBD80 datasheet
 


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NXP Semiconductors
On the LPC1759/58/56/54/52/51, I/O pads are powered by the 3.3 V (V
the V
DD(REG)(3V3)
the CPU and most of the peripherals.
Depending on the LPC1759/58/56/54/52/51 application, a design can use two power
options to manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
DD(3V3)
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(V
DD(REG)(3V3)
there is no power drain from the RTC battery when V
LPC1759_58_56_54_52_51
Product data sheet
pin powers the on-chip voltage regulator which in turn provides power to
and V
pins together. This approach requires only one 3.3 V power
DD(REG)(3V3)
) is used to operate the RTC whenever V
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
). Having the on-chip voltage regulator
DD(REG)(3V3)
is present. Therefore,
DD(REG)(3V3)
is available.
DD(REG)(3V3)
) pins, while
DD(3V3)
) and
DD(3V3)
© NXP B.V. 2011. All rights reserved.
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