The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part NumberLPC1759FBD80
DescriptionThe LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
ManufacturerNXP Semiconductors
LPC1759FBD80 datasheet
 


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NXP Semiconductors
2
11.5 I
C-bus
Table 12.
T
=
amb
Symbol
f
SCL
t
f
t
LOW
t
HIGH
t
HD;DAT
t
SU;DAT
[1]
See the I
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
t
HD;DAT
and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
IH
[5]
C
= total capacitance of one bus line in pF.
b
[6]
The maximum t
output stage t
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8]
The maximum t
the maximum of t
maximum must only be met if the device does not stretch the LOW period (t
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
t
SU;DAT
transmission and the acknowledge.
LPC1759_58_56_54_52_51
Product data sheet
2
Dynamic characteristic: I
C-bus pins
[2]
40
C to +85
C.
Parameter
Conditions
SCL clock
Standard-mode
frequency
Fast-mode
[4][5][6][7]
fall time
of both SDA and
SCL signals
LOW period of
Standard-mode
the SCL clock
Fast-mode
HIGH period of
Standard-mode
the SCL clock
Fast-mode
[3][4][8]
data hold time
Standard-mode
Fast-mode
[9]
data set-up
Standard-mode
time
Fast-mode
2
C-bus specification UM10204 for details.
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
f
is specified at 250 ns. This allows series protection resistors to be connected in between the
f
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
HD;DAT
or t
by a transition time (see the I
VD;DAT
VD;ACK
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
[1]
Min
0
0
-
Standard-mode
20 + 0.1  C
Fast-mode
b
4.7
1.3
4.0
0.6
0
0
250
100
2
C-bus specification UM10204). This
) of the SCL signal. If the
LOW
Max
Unit
100
kHz
400
kHz
300
ns
300
ns
s
-
s
-
s
-
s
-
s
-
s
-
-
ns
-
ns
.
f
© NXP B.V. 2011. All rights reserved.
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