LPC1765FET100 NXP Semiconductors, LPC1765FET100 Datasheet - Page 68

• Manufacturer Part Number: LPC1765FET100
• Description: The LPC1765 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 100 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
Fig 32. USB device port configuration
14.2 Crystal oscillator XTAL input and component selection
LPC17xx
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
C
capacitor to ground C
mode, a minimum of 200 mV(RMS) is needed.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in
Table 22
and the capacitances C
fundamental mode oscillation (the fundamental frequency is represented by L, C
R
not be larger than 7 pF. Parameters F
manufacturer.
Fig 33. Slave mode operation of the on-chip oscillator
i
S
= 100 pF. To limit the input voltage to the specified range, choose an additional
). Capacitance C
USB_UP_LED
USB_CONNECT
USB_D+
USB_D−
V
BUS
33), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
and
Table
All information provided in this document is subject to legal disclaimers.
33 Ω
33 Ω
P
23. Since the feedback resistance is integrated on chip, only a crystal
in
g
Rev. 8 — 14 November 2011
V
which attenuates the input voltage by a factor C
Figure 34
X1
DD
and C
V
DD
X2
LPC1769/68/67/66/65/64/63
represents the parallel package capacitance and should
need to be connected externally in case of
OSC
XTAL1
LPC1xxx
C i
100 pF
, C
L
, R
S
002aae835
32-bit ARM Cortex-M3 microcontroller
C g
and C
P
are supplied by the crystal
V
SS
V
BUS
D+
D−
USB-B
connector
002aad943
i
/(C
© NXP B.V. 2011. All rights reserved.
Figure 34
i
+ C
g
). In slave
L
and
and in
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