LPC1788FBD144 NXP Semiconductors, LPC1788FBD144 Datasheet

The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1788FBD144

Manufacturer Part Number
LPC1788FBD144
Description
The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features and benefits
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation.
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at
the same clock rate and other system enhancements such as modernized debug features
and a higher level of support block integration. The Cortex-M3 CPU incorporates a
3-stage pipeline and has a Harvard architecture with separate local instruction and data
buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC178x/7x operates at up to
120 MHz CPU frequency.
The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB
Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,
three I
Encoder Interface, four general purpose timers, two general purpose PWMs with six
outputs each and one motor control PWM, an ultra-low power RTC with separate battery
supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to
165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow
pin function compatibility with the LPC24xx and LPC23xx.
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC
Rev. 3 — 27 December 2011
Functional replacement for the LPC23xx and LPC24xx family devices.
System:
2
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU,USB, Ethernet, and the General Purpose DMA
controller. This interconnect provides communication with no arbitration delays
unless two masters attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature
Objective data sheet

Related parts for LPC1788FBD144

LPC1788FBD144 Summary of contents

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LPC178x/7x 32-bit ARM Cortex-M3 microcontroller 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 3 — 27 December 2011 1. General description The LPC178x/ ARM Cortex-M3 based microcontroller for embedded applications requiring ...

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... NXP Semiconductors  Cortex-M3 system tick timer, including an external clock input option.  Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options.  Emulation trace module supports real-time trace.  Boundary scan for simplified board testing.  ...

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... NXP Semiconductors  CAN controller with two channels.  Digital peripherals:  SD/MMC memory card interface.  165 General Purpose I/O (GPIO) pins depending on the packaging with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M3 bit-banding ...

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... NXP Semiconductors  Clock generation:  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be used as a system clock.  ...

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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name LPC1788 LPC1788FBD208 LQFP208 LPC1788FET208 TFBGA208 LPC1788FET180 TFBGA180 LPC1788FBD144 LQFP144 LPC1787 LPC1787FBD208 LQFP208 LPC1786 LPC1786FBD208 LQFP208 LPC1785 LPC1785FBD208 LQFP208 LPC1778 LPC1778FBD208 LQFP208 LPC1778FET208 TFBGA208 LPC1778FET180 TFBGA180 LPC1778FBD144 LQFP144 LPC1777 LPC1777FBD208 LQFP208 ...

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... All parts include two CAN channels, three SSP interfaces, three I 12-bit ADC. Type number Flash CPU (kB) SRAM (kB) LPC178x LPC1788FBD208 512 64 LPC1788FET208 512 64 LPC1788FET180 512 64 LPC1788FBD144 512 64 LPC1787FBD208 512 64 LPC1786FBD208 256 64 LPC1785FBD208 256 64 LPC177x LPC1778FBD208 512 64 LPC1778FET208 512 64 LPC1778FET180 512 64 LPC1778FBD144 512 ...

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... NXP Semiconductors 5. Block diagram debug port I-code bus slave EMC slave (1) LCD slave HIGH-SPEED GPIO APB slave group 0 WINDOWED WDT PIN CONNECT GPIO INTERRUPT CONTROL EVENT RECORDER 32 kHz OSCILLATOR BACKUP REGISTERS RTC POWER DOMAIN (1) Not available on all parts. See Fig 1. Block diagram ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. LPC178X_7X Objective data sheet 1 LPC178x/7xFBD208 52 Pin configuration (LQFP208) ball A1 index area Pin configuration (TFBGA208) All information provided in this document is subject to legal disclaimers. Rev. 3 — 27 December 2011 ...

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... NXP Semiconductors Fig 4. Fig 5. 6.2 Pin description I/O pins on the LPC178x/7x are 5V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP) ...

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... NXP Semiconductors Table 3. Pin description Not all functions are available on all parts. See pins). Symbol P0[0] to P0[31] P0[0] 94 U15 M10 66 P0[1] 96 T14 N11 P0[2] 202 C4 D5 P0[3] 204 D6 A3 P0[4] 168 B12 A11 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[5] 166 C12 B11 P0[6] 164 D13 D11 P0[7] 162 C13 B12 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [3] 115 I; I/O P0[5] — General purpose digital input/output pin. ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[8] 160 A15 C12 111 P0[9] 158 C14 A13 P0[10] 98 T15 L10 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [ I/O P0[8] — General purpose digital input/output pin. ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[11] 100 R14 P12 P0[12 P0[13 P0[14 P0[15] 128 J16 H13 89 P0[16] 130 J14 H14 90 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[17] 126 K17 J12 P0[18] 124 K15 J13 P0[19] 122 L17 J10 P0[20] 120 M17 K14 P0[21] 118 M16 K11 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[22] 116 N17 L14 P0[23 P0[24 P0[25 P0[26 P0[27 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [ ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P0[28 P0[29 P0[30 P0[31 P1[0] to P1[31] P1[0] 196 A3 B5 P1[1] 194 B5 A5 P1[2] 185 D9 B7 P1[3] 177 A10 A9 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[4] 192 A5 C6 P1[5] 156 A17 B13 P1[6] 171 B11 B10 P1[7] 153 D14 C13 - P1[8] 190 C7 B6 P1[9] 188 A6 D7 P1[10] 186 C8 A7 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[11] 163 A14 A12 P1[12] 157 A16 A14 P1[13] 147 D16 D14 - P1[14] 184 A7 D8 P1[15] 182 A8 A8 P1[16] 180 D10 B8 P1[17] 178 A9 C9 P1[18 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[19 P1[20 P1[21 P1[22 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [ I/O P1[19] — General purpose digital input/output pin. ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[23 P1[24 P1[25] 80 T10 L7 P1[26] 82 R10 P8 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [ I/O P1[23] — General purpose digital input/output pin. ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[27] 88 T12 M9 P1[28] 90 T13 P10 P1[29] 92 U14 N10 64 P1[30 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [ I/O P1[27] — General purpose digital input/output pin. ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[31 P2[0] to P2[31] P2[0] 154 B17 D12 107 P2[1] 152 E14 C14 106 P2[2] 150 D15 E11 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[3] 144 E16 E13 P2[4] 142 D17 E14 P2[5] 140 F16 F12 P2[6] 138 E17 F13 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[7] 136 G16 G11 95 P2[8] 134 H15 G14 93 P2[9] 132 H16 H11 P2[10] 110 N15 M13 76 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[11] 108 T17 M12 75 P2[12] 106 N14 N14 73 P2[13] 102 T16 M11 71 P2[14] 91 R12 - LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description [10] I ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[15] 99 P13 - P2[16] 87 R11 P9 P2[17] 95 R13 P11 P2[18 P2[19 P2[20 P2[21] 81 U11 N8 P2[22] 85 U12 - P2[23 P2[24 P2[25 P2[26 LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[27 P2[28 P2[29 P2[30 P2[31 P3[0] to P3[31] P3[0] 197 B4 D6 P3[1] 201 B3 E6 P3[2] 207 B1 A2 P3[ P3[ P3[ LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[ P3[ P3[8] 191 D8 A6 P3[9] 199 C5 A4 P3[10] 205 B2 B3 P3[11] 208 D5 B2 P3[12 P3[13 P3[14 P3[15 P3[16] 137 F17 - P3[17] 143 F15 - P3[18] 151 C15 - P3[19] 161 B14 ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[20] 167 A13 - P3[21] 175 C10 - P3[22] 195 C6 - P3[23 P3[24 P3[25 P3[26 P3[27] 203 A1 - LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P3[28 P3[29 P3[30 P3[31 P4[0] to P4[31] P4[ P4[1] 79 U10 M7 P4[2] 83 T11 M8 P4[3] 97 U16 K9 P4[4] 103 R15 P13 P4[5] 107 R16 H10 74 P4[6] 113 M14 K10 P4[7] 121 L16 K12 LPC178X_7X Objective data sheet ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[8] 127 J17 J11 P4[9] 131 H17 H12 91 P4[10] 135 G17 G12 94 P4[11] 145 F14 F11 P4[12] 149 C16 F10 P4[13] 155 B16 B14 P4[14] 159 B15 E8 P4[15] 173 A11 C10 120 P4[16] 101 U17 ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[22] 123 K14 - P4[23] 129 J15 - P4[24] 183 B8 C8 P4[25] 179 B9 D9 P4[26] 119 L15 K13 P4[27] 139 G15 F14 P4[28] 170 C11 D10 118 P4[29] 176 B10 B9 P4[30] 187 B7 C7 LPC178X_7X Objective data sheet ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[31] 193 A4 E7 P5[0] to P5[4] P5[ P5[ P5[2] 117 L14 L12 P5[3] 141 G14 G10 98 P5[4] 206 C3 C4 JTAG_TDO (SWO) JTAG_TDI LPC178X_7X Objective data sheet Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol JTAG_TMS (SWDIO) JTAG_TRST JTAG_TCK (SWDCLK) RESET RSTOUT RTC_ALARM RTCX1 RTCX2 USB_D VBAT 26, ...

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... NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol V 33, L3, H4, SS 63, T5, P4, 77, R9, L9, 93, P12, L13, 114, N16, G13, 133, H14, D13, 148, E15, C11, 169, A12, B4 189, B6, 200 A2 V 32, D12, H3, SSREG 84, ...

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... NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row A 1 P3[27 P1[ P1[17 P3[20 P1[5] Row B 1 P3[ P1[ P4[25 DD(3V3) 17 P2[0] Row C 1 P3[13 P3[ DD(3V3) 13 P0[ DD(3V3 ...

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... NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol P4[10] Row H 1 P0[23 P4[9] Row J 1 P3[ P4[8] Row K 1 VREFP P0[17] Row L 1 P3[ ...

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... NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol 9 P1[23 P2[15 DD(3V3) Row R 1 P0[12 P3[24 P2[17 P4[20] Row T 1 P0[27 P1[24 P1[28 P2[11] Row U 1 USB_D P2[23] ...

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... NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol 5 P0[ P4[25 Row E 1 P0[24 P5[ DD(REG)(3V3) 13 P2[3] 14 Row F 1 P3[14 P0[23 P2[6] 14 Row DD(REG)(3V3) ...

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... NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row J 1 RESET 2 5 P0[13 P0[18] 14 Row K 1 VBAT 2 5 P0[29 P4[ P4[26] 14 Row L 1 P2[29 P1[18 Row M 1 P0[28 P0[14] ...

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... NXP Semiconductors The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption ...

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... NXP Semiconductors The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place ...

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APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved (1) 16 SD/MMC 0x400C 0000 (1) 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 reserved 13 0x400B 4000 12 reserved 0x400B 0000 SSP2 11 0x400A ...

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... NXP Semiconductors 7.8 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.8.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC178x/7x, the NVIC supports 40 vectored interrupts. ...

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... NXP Semiconductors Table 7. External memory controller pin configuration Part Data bus pins Address bus LPC1788FBD208 EMC_D[31:0] LPC1788FET208 EMC_D[31:0] LPC1788FET180 EMC_D[15:0] LPC1788FBD144 EMC_D[7:0] LPC1787FBD208 EMC_D[31:0] LPC1786FBD208 EMC_D[31:0] LPC1785FBD208 EMC_D[31:0] LPC1778FBD208 EMC_D[31:0] LPC1778FET208 EMC_D[31:0] LPC1778FET180 EMC_D[15:0] LPC1778FBD144 EMC_D[7:0] LPC1777FBD208 EMC_D[31:0] LPC1776FBD208 EMC_D[31:0] LPC1776FET180 ...

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... NXP Semiconductors The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral ...

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... NXP Semiconductors 7.11.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • ...

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... NXP Semiconductors • Accept any size of data width per write 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle) 7.13 LCD controller Remark: The LCD controller is available on parts LPC1788/87/86/85. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024  ...

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... NXP Semiconductors 7.14 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...

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... NXP Semiconductors – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.15 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85 and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774. The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals ...

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... NXP Semiconductors • Supports per-port power switching 7.15.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I interface to implement OTG dual-role device functionality ...

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... NXP Semiconductors • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. ...

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... NXP Semiconductors 7.19.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support 7.20 UARTs Remark: USART4 is not available on part LPC1774FBD144. The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data ...

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... NXP Semiconductors during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. ...

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... NXP Semiconductors 2 7.23 I S-bus serial I/O controllers The LPC178x/7x contain one I communication interface for digital audio applications. 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave ...

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... NXP Semiconductors • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.25 General purpose 32-bit timers/external event counters The LPC178x/7x include four 32-bit timer/counters. ...

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... NXP Semiconductors Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs ...

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... NXP Semiconductors PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2 Table 8 ...

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... NXP Semiconductors 7.30 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.30.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • ...

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... NXP Semiconductors • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. ...

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... NXP Semiconductors Fig 7. 7.33.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source. ...

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... NXP Semiconductors 7.33.1.3 RTC oscillator The RTC oscillator provides clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.33.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled ...

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... NXP Semiconductors 7.33.3 Wake-up timer The LPC178x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

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... NXP Semiconductors The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. ...

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... NXP Semiconductors 7.33.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator ...

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... NXP Semiconductors The second option uses two power supplies; a 3.3 V supply for the I/O pads (V a dedicated 3.3 V supply for the CPU (V powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly” while the CPU and peripherals stay active. ...

Page 67

... NXP Semiconductors 7.34 System control 7.34.1 Reset Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating ...

Page 68

... NXP Semiconductors CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.34.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller ...

Page 69

... NXP Semiconductors 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREFP i(VREFP) ...

Page 70

... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • Table 10. Thermal characteristics = 40 C to +85 C unless otherwise specified 3 3 amb Symbol Parameter T maximum junction j(max) temperature Table 11.  amb ja  ...

Page 71

... NXP Semiconductors Table 12.  amb ja jc jb LPC178X_7X Objective data sheet Thermal resistance value (TFBGA packages)   +85 C unless otherwise specified. JEDEC (4.5 in  4 in) 0 m/s 1 m/s 2.5 m/s 8-layer (4.5 in  3 in) 0 m/s 1 m/s 2.5 m/s All information provided in this document is subject to legal disclaimers. Rev. 3 — 27 December 2011 ...

Page 72

... NXP Semiconductors 10. Static characteristics Table 13. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...

Page 73

... NXP Semiconductors Table 13. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output ...

Page 74

... NXP Semiconductors Table 13. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage for low-/full-speed V HIGH-level output OH voltage (driven) for low-/full-speed C transceiver capacitance pin to GND trans Oscillator pins (see Section 14 ...

Page 75

... NXP Semiconductors 10.1 Power consumption I DD(REG)(3V3) Fig 9. I DD(REG)(3V3) Fig 10. Power-down mode: Regulator supply current I LPC178X_7X Objective data sheet 600 (μA) 500 V = 3.6 V DD(REG)(3V3) 3.3 V 3.0 V 2.4 V 400 300 -40 -15 10 Conditions: BOD disabled. Deep-sleep mode: Regulator supply current I 300 (μA) 200 ...

Page 76

... NXP Semiconductors 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, ...

Page 77

... NXP Semiconductors Table 14 amb Peripheral EMC RTC USB + PLL1 Ethernet [1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470). [2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470). LPC178X_7X Objective data sheet Power consumption for individual analog and digital blocks  ...

Page 78

... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 11. Typical HIGH-level output voltage V (mA) Fig 12. Typical LOW-level output current I LPC178X_7X Objective data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions DD(REG)(3V3) DD(3V3 0.2 Conditions DD(REG)(3V3) DD(3V3) All information provided in this document is subject to legal disclaimers. Rev. 3 — ...

Page 79

... NXP Semiconductors Fig 13. Typical pull-up current I (μA) Fig 14. Typical pull-down current I LPC178X_7X Objective data sheet (μA) −10 − °C 25 °C −40 °C −50 − Conditions DD(REG)(3V3) DD(3V3) versus input voltage ° °C − ...

Page 80

... NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 15.  amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 16.  amb Symbol ...

Page 81

... NXP Semiconductors 11.2 External memory interface Table 17. Dynamic characteristics: Static external memory interface    pF amb [1] Symbol Parameter [2] Read cycle parameters t CS LOW to address valid CSLAV time t CS LOW to OE LOW time CSLOEL t CS LOW to BLS LOW time ...

Page 82

... NXP Semiconductors Table 17. Dynamic characteristics: Static external memory interface    pF amb [1] Symbol Parameter t BLS LOW to BLS HIGH time WR BLSLBLSH t BLS HIGH to end of write BLSHEOW time t BLS HIGH to data invalid BLSHDNV time [1] Parameters are shown as RD ...

Page 83

... NXP Semiconductors EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx Fig 16. External static memory read/write access (PB =1) EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx Fig 17. External static memory burst read cycle Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits   ...

Page 84

... NXP Semiconductors Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits    pF amb Values guaranteed by design. Symbol Parameter t column address strobe hold time h(CAS) t write valid delay time d(WV) t write hold time h(W) t address valid delay time ...

Page 85

... NXP Semiconductors [2] The data input set-up time has to be selected with the following margin: + delay time of feedback clock  SDRAM access time  board delay time  su(D) [3] The data input hold time has to be selected with the following margin: + SDRAM access time - board delay time - delay time of feedback clock  0. ...

Page 86

... NXP Semiconductors 11.3 External clock Table 21.  amb Symbol f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 19. External clock timing (with an amplitude of at least V 11 ...

Page 87

... NXP Semiconductors Fig 20. Internal RC oscillator frequency versus temperature 11.5 I/O pins Table 23.  amb Symbol [1] Applies to standard port pins and RESET pin. For details, see the LPC178x/7x IBIS model available on the NXP website. 11.6 SSP interface Table 24.  amb Symbol SSP master ...

Page 88

... NXP Semiconductors Table 24.  amb Symbol T cy(PCLK) T cy(clk v(Q) t h(Q) [1] T cy(clk) T cy(clk) SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). [2] T amb [3] T cy(clk) [4] T amb SCK (CPOL = 0) SCK (CPOL = 1) Fig 21 ...

Page 89

... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SSP slave timing in SPI mode 2 11.7 I C-bus Table 25.  amb Symbol f SCL LOW t HIGH LPC178X_7X Objective data sheet T cy(clk) MOSI DATA VALID MISO DATA VALID MOSI DATA VALID t v(Q) MISO DATA VALID 2 Dynamic characteristic: I C-bus pins  ...

Page 90

... NXP Semiconductors Table 25.  amb Symbol t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. [3] t HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL ...

Page 91

... NXP Semiconductors 2 11.8 I S-bus interface Table 26.  amb Symbol common to input and output output t v(Q) input t su(D) t h(D) [1] CCLK = 100 MHz; peripheral clock to the I 1600 ns, corresponds to the SCK signal in the I I2S_TX_SCK I2S_TX_SDA I2S_TX_WS Fig 24. I LPC178X_7X Objective data sheet ...

Page 92

... NXP Semiconductors I2S_RX_SCK I2S_RX_SDA I2S_RX_WS Fig 25. I 11.9 USB Table 27. Dynamic characteristics of USB pins (full-speed)  pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP ...

Page 93

... NXP Semiconductors T PERIOD differential data lines Fig 26. Differential data-to-EOP transition skew and EOP width 11.10 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. Table 28.  amb Symbol Parameter RMII mode f clk d clk MII mode f clk d clk t su ...

Page 94

... NXP Semiconductors Fig 27. Ethernet timing 11.11 LCD Remark: The LCD controller is available on parts LPC1788/87/86/85. Table 29. Values listed describe design constraints. Symbol T cy(clk) 11.12 SD/MMC Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts LPC1778/77/76. Table 30.  amb Symbol f clk t su(D) t h(D) t d(QV) t h(Q) LPC178X_7X ...

Page 95

... NXP Semiconductors Fig 28. SD/MMC timing 12. ADC electrical characteristics Table DDA Symbol V IA 12-bit resolution; 400 kSamples/sec L(adj clk(ADC) f c(ADC vsi 8-bit resolution L(adj clk(ADC) LPC178X_7X Objective data sheet SD_CLK ...

Page 96

... NXP Semiconductors Table DDA Symbol f c(ADC vsi [1] Conditions: V [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (E See [4] The integral non-linearity (E the ideal transfer curve after appropriate adjustment of gain and offset errors. See [5] The offset error (E straight line which fits the ideal curve ...

Page 97

... NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...

Page 98

... NXP Semiconductors Fig 30. ADC interface to pins ADC0_IN[n] Table 32. Component R cmp 13. DAC electrical characteristics Table DDA Symbol L(adj LPC178X_7X Objective data sheet LPC178x/ cmp 90 Ω - 300 Ω 1.6 pF ADC COMPARATOR BLOCK ...

Page 99

... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774. LPC17xx Fig 31. USB interface on a self-powered device LPC17xx Fig 32. USB interface on a bus-powered device LPC178X_7X Objective data sheet ...

Page 100

... NXP Semiconductors RSTOUT V R4 USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D-1 USB_UP_LED1 LPC178x/7x USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 33 Ω 33 Ω USB_D-2 USB_UP_LED2 Fig 33. USB OTG port configuration: port 1 OTG dual-role device, port 2 host LPC178X_7X Objective data sheet RESET_N ADR/PSW OE_N/INT_N DD SPEED ...

Page 101

... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC178x/7x USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 34. USB OTG port configuration: VP_VM mode LPC178X_7X Objective data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N V DD All information provided in this document is subject to legal disclaimers. Rev. 3 — ...

Page 102

... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D-1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC178x/7x USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D-2 USB_UP_LED2 Fig 35. USB host port configuration: port 1 and port 2 as hosts LPC178X_7X Objective data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA LM3526-L ENB 33 Ω ...

Page 103

... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D-1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC178x/7x USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D-2 V BUS Fig 36. USB device port configuration: port 1 host and port 2 device 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a ...

Page 104

... NXP Semiconductors Fig 37. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...

Page 105

... NXP Semiconductors Table 34. Fundamental oscillation frequency F 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 35. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 14.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane ...

Page 106

... NXP Semiconductors pin configured as digital output pin configured as digital input pin configured as analog input Fig 39. Standard I/O pin configuration with analog input 14.5 Reset pin configuration Fig 40. Reset pin configuration 14.6 Reset pin configuration for RTC operation Under certain circumstances, the RTC may temporarily pause and lose fractions of a second during the rising and falling edges of the RESET signal ...

Page 107

... NXP Semiconductors To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal, connect an RC filter between the RESET pin and the external reset input. Fig 41. Reset input with RC filter LPC178X_7X Objective data sheet 10 kΩ RESET pin 0.1 μ ...

Page 108

... NXP Semiconductors 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 109

... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.6 0.4 OUTLINE ...

Page 110

... NXP Semiconductors TFBGA180: thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions UNIT 1 2 max. 0.35 0.85 0.5 mm 1.2 0.25 0.75 0.4 OUTLINE VERSION ...

Page 111

... NXP Semiconductors LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 112

... NXP Semiconductors 16. Soldering Footprint information for reflow soldering of LQFP208 package solder land occupied area DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 46. Reflow soldering of the LQFP208 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× ...

Page 113

... NXP Semiconductors Footprint information for reflow soldering of TFBGA180 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.400 0.400 0.550 12.575 12.575 Fig 47. Reflow soldering of the TFBGA180 package LPC178X_7X Objective data sheet ...

Page 114

... NXP Semiconductors Footprint information for reflow soldering of LQFP144 package solder land occupied area DIMENSIONS 0.500 0.560 23.300 23.300 20.300 20.300 Fig 48. Reflow soldering of the LQFP144 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern ...

Page 115

... NXP Semiconductors 17. Abbreviations Table 36. Acronym ADC AHB AMBA APB BOD CAN DAC DMA EOP ETM GPIO GPS HVAC IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLC PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB LPC178X_7X Objective data sheet ...

Page 116

... NXP Semiconductors 18. Revision history Table 37. Revision history Document ID Release date LPC178X_7X v.3 20111227 • Modifications: Removed BOOT function from pin P3[14]. • I • Maximum SDRAM clock of 80 MHz specified in • Power consumption data added • Removed parameter Z • Specified maximum value for parameter C • ...

Page 117

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 118

... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 119

... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 40 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 40 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 41 7.3 On-chip flash program memory . . . . . . . . . . . 41 7.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6 Memory Protection Unit (MPU ...

Page 120

... NXP Semiconductors 8 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . 70 10 Static characteristics 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 75 10.2 Peripheral power consumption . . . . . . . . . . . . 76 10.3 Electrical pin characteristics . . . . . . . . . . . . . . 78 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 80 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2 External memory interface . . . . . . . . . . . . . . . 81 11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.4 Internal oscillators 11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 87 2 11.7 I C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2 11.8 I S-bus interface . . . . . . . . . . . . . . . . . . . . . . . 91 11.9 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.11 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11 ...

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