LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet
LPC1850FET256
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LPC1850FET256 Summary of contents
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LPC1850/30/20/10 32-bit ARM Cortex-M3 MCU 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller Rev. 3.1 — 15 December 2011 1. General description The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM ...
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... NXP Semiconductors Ultra-low power RTC crystal oscillator. Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL. Clock output. ...
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... NXP Semiconductors Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. Four general-purpose timer/counters with capture and match capabilities. One motor control PWM for three-phase motor control. One Quadrature Encoder Interface (QEI). ...
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... LPC1810FET100 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm LPC1810FBD144 LQFP144 4.1 Ordering options Table 2. Ordering options Type number Total LCD Ethernet USB0 SRAM LPC1850FET256 200 kB yes LPC1850FET180 200 kB yes LPC1850FBD208 200 kB yes LPC1830FET256 200 kB no LPC1830FET180 200 kB no ...
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... NXP Semiconductors 5. Block diagram SWD/TRACE PORT/JTAG TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 BRIDGE 0 BRIDGE 1 BRIDGE 2 MOTOR RI TIMER WWDT CONTROL (1) USART0 PWM UART1 SSP0 TIMER0 C_CAN1 TIMER1 SCU GPIO interrupts GPIO GROUP0 interrupt GPIO GROUP1 interrupt = connected to GPDMA (1) Not available on all parts (see Fig 1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning LPC1850/30FET256 ball A1 index area Transparent top view Fig 2. Pin configuration LBGA256 package Fig 4. Pin configuration TFBGA100 package LPC1850_30_20_10 Preliminary data sheet ball A1 index area ...
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... NXP Semiconductors 1 LPC1850FBD208 52 Fig 5. Pin configuration LQFP208 package Fig 7. Pin configuration LQFP100 package 6.2 Pin description On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named and PA to PF, with pins used per port. Each digital pin can support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the SCU registers ...
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... NXP Semiconductors Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol Multiplexed digital pins P0_0 P0_1 P1_0 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO0[0] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_1 P1_2 P1_3 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see O CTOUT_7 — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_4 P1_5 P1_6 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO0[11] — General purpose digital input/output pin. O CTOUT_9 — SCT output 9. Match output 1 of timer 2 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_7 P1_8 P1_9 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO1[0] — General purpose digital input/output pin. I U1_DSR — Data Set Ready input for UART1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_10 P1_11 P1_12 P1_13 R10 x H8 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO1[3] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_14 R11 x J8 P1_15 T12 x K8 P1_16 P1_17 M8 x H10 93 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO1[7] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_18 N12 x J10 P1_19 M11 x K9 P1_20 M10 x K10 100 70 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO0[13] — General purpose digital input/output pin. I/O U2_DIR — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_0 T16 x G10 108 75 P2_1 N15 x G7 P2_2 M15 x F5 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. O U0_TXD — Transmitter output for USART0. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_3 J12 x D8 P2_4 K11 x D9 P2_5 K14 x D10 131 91 LPC1850_30_20_10 Preliminary data sheet Description [4] 127 — Function reserved. I/O I2C1_SDA — I ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_6 K16 x G9 P2_7 H14 x C10 138 96 P2_8 J16 x C6 LPC1850_30_20_10 Preliminary data sheet Description [3] 137 — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O EMC_A10 — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_9 H16 x B10 144 102 70 P2_10 G16 x E8 P2_11 F16 x A9 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO1[10] — General purpose digital input/output pin ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_12 E15 x B9 P2_13 C16 x A10 156 108 75 P3_0 F13 x A8 LPC1850_30_20_10 Preliminary data sheet Description [3] 153 106 I/O GPIO1[12] — General purpose digital input/output pin ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_1 G11 x F7 P3_2 F11 x G6 P3_3 B14 x A7 LPC1850_30_20_10 Preliminary data sheet Description [3] 163 114 I/O I2S0_TX_WS — Transmit Word Select driven by the master and received by the slave ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_4 A15 x B8 P3_5 C12 x B7 P3_6 B13 x C7 LPC1850_30_20_10 Preliminary data sheet Description [3] 171 119 I/O GPIO1[14] — General purpose digital input/output pin ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_7 C11 x D7 P3_8 C10 x E7 P4_0 P4_1 LPC1850_30_20_10 Preliminary data sheet Description [3] 176 123 — Function reserved. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_2 P4_3 P4_4 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO2[2] — General purpose digital input/output pin. O CTOUT_0 — SCT output 0. Match output 0 of timer 0 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_5 P4_6 P4_7 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO2[5] — General purpose digital input/output pin. O CTOUT_5 — SCT output 5. Match output 1 of timer 1 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_8 P4_9 P4_10 P5_0 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P5_1 P5_2 P5_3 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO2[10] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P5_4 P5_5 P10 x - P5_6 T13 x - P5_7 R12 x - LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO2[13] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_0 M12 x H7 P6_1 R15 x G5 P6_2 L13 x J9 LPC1850_30_20_10 Preliminary data sheet Description [3] 105 — Function reserved. O I2S0_RX_MCLK — — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_3 P15 x - P6_4 R16 x F6 P6_5 P16 x F9 LPC1850_30_20_10 Preliminary data sheet Description [3] 113 I/O GPIO3[2] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_6 L14 x - P6_7 J13 x - P6_8 H13 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 119 I/O GPIO0[5] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_9 J15 x F8 P6_10 H15 x - P6_11 H12 x C9 P6_12 G15 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 139 I/O GPIO3[5] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P7_0 B16 x - P7_1 C14 x - P7_2 A16 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 158 110 - I; PU I/O GPIO3[8] — General purpose digital input/output pin. O CTOUT_14 — SCT output 14. Match output 2 of timer 3 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P7_3 C13 x - P7_4 P7_5 LPC1850_30_20_10 Preliminary data sheet Description [3] 167 117 - I; PU I/O GPIO3[11] — General purpose digital input/output pin. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P7_6 P7_7 P8_0 LPC1850_30_20_10 Preliminary data sheet Description [3] 194 134 - I; PU I/O GPIO3[14] — General purpose digital input/output pin. O CTOUT_11 — SCT output 1. Match output 3 of timer 2 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P8_1 P8_2 P8_3 P8_4 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO4[1] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P8_5 P8_6 P8_7 P8_8 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO4[5] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P9_0 P9_1 P9_2 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO4[12] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P9_3 P9_4 N10 x - P9_5 LPC1850_30_20_10 Preliminary data sheet Description [ I/O GPIO4[15] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P9_6 L11 x - PA_0 L12 x - PA_1 J14 x - PA_2 K15 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 103 I/O GPIO4[11] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PA_3 H11 x - PA_4 G13 x - PB_0 B15 x - LPC1850_30_20_10 Preliminary data sheet Description [4] 147 - - I; PU I/O GPIO4[10] — General purpose digital input/output pin. I QEI_PHA — Quadrature Encoder Interface PHA input ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PB_1 A14 x - PB_2 B12 x - PB_3 A13 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 175 - - — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PB_4 B11 x - PB_5 A12 x - PB_6 LPC1850_30_20_10 Preliminary data sheet Description [3] 180 - - — Function reserved. I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_0 PC_1 PC_2 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_3 PC_4 PC_5 LPC1850_30_20_10 Preliminary data sheet Description [ I/O USB1_ULPI_D5 — ULPI link bidirectional data line — Function reserved. O U1_RTS — Request to Send output for UART1. Can also be configured RS-485/EIA-485 output enable signal for UART1 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_6 PC_7 PC_8 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line — Function reserved. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_9 PC_10 PC_11 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_12 PC_13 PC_14 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved — Function reserved. O U1_DTR — Data Terminal Ready output for UART1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_0 PD_1 PD_2 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. O EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_3 PD_4 PD_5 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. O CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_6 PD_7 PD_8 PD_9 T11 - - LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. O CTOUT_10 — SCT output 10. Match output 2 of timer 2. I/O EMC_D20 — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_10 P11 - - PD_11 PD_12 N11 x - LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I CTIN_1 — SCT input 1. Capture input 1 of timer 0. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_13 T14 x - PD_14 R13 x - PD_15 T15 x - LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I CTIN_0 — SCT input 0. Capture input 0 of timer ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_16 R14 x - PE_0 P14 x - PE_1 N14 x - PE_2 M14 x - LPC1850_30_20_10 Preliminary data sheet Description [3] 104 - - — Function reserved — Function reserved. I/O EMC_A16 — External memory address line 16. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_3 K12 x - PE_4 K13 x - PE_5 N16 - - PE_6 M16 - - LPC1850_30_20_10 Preliminary data sheet Description [3] 118 - - — Function reserved. O CAN0_TD — CAN transmitter output. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_7 F15 - - PE_8 F14 - - PE_9 E16 - - PE_10 E14 - - LPC1850_30_20_10 Preliminary data sheet Description [3] 149 - - — Function reserved. O CTOUT_5 — SCT output 5. Match output 1 of timer 1 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_11 D16 - - PE_12 D15 - - PE_13 G14 - - LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. O CTOUT_12 — SCT output 12. Match output 0 of timer 3 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_14 C15 - - PE_15 E13 - - PF_0 D12 - - PF_1 E11 - - LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved — Function reserved — Function reserved. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_2 D11 - - PF_3 E10 - - PF_4 D10 x H4 LPC1850_30_20_10 Preliminary data sheet Description [3] 168 - - — Function reserved. O U3_TXD — Transmitter output for USART3. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_5 PF_6 PF_7 LPC1850_30_20_10 Preliminary data sheet Description [6] 190 - - — Function reserved. I/O U3_UCLK — Serial clock input/output for USART3 in synchronous mode. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_8 PF_9 PF_10 LPC1850_30_20_10 Preliminary data sheet Description [ — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_11 Clock pins CLK0 CLK1 T10 x - LPC1850_30_20_10 Preliminary data sheet Description [6] 207 - 100 — Function reserved. I U0_RXD — Receiver input for USART0. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol CLK2 D14 x K6 CLK3 P12 x - Debug pins DBGEN TCK/SWDCLK TRST TMS/SWDIO TDO/SWO TDI USB0 pins USB0_DP ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol USB0_ID USB0_RREF USB1 pins USB1_DP F12 x E9 USB1_DM G12 x E10 130 C-bus pins I2C0_SCL L15 x D6 I2C0_SDA L16 x E6 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol ADC0_5 ADC1_5 ADC0_6 ADC1_6 ADC0_7 ADC1_7 RTC RTC_ALARM A11 x C3 RTCX1 RTCX2 Crystal oscillator pins XTAL1 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol VDDIO D7, x F10, E12, K5 F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 VDD - - - VSS G9, x C8, H7, D4, J10, D5, J11, G8, K8 J3, J6 VSSIO C4 D13, ...
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... NXP Semiconductors [ tolerant pad with 15 ns glitch filter (5 V tolerant if V functions with TTL levels and hysteresis; normal drive strength (see [ tolerant pad with 15 ns glitch filter (5 V tolerant if V functions with TTL levels, and hysteresis; high drive strength (see ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-CODE bus, and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3 ...
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... NXP Semiconductors 7.3 AHB multilayer matrix TEST/DEBUG INTERFACE ARM CORTEX-M3 GPDMA System I-code D-code 0 bus bus bus AHB MULTILAYER MATRIX = master-slave connection (1) Not available on all parts (see Fig 8. AHB multilayer matrix master and slave connections 7.4 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors 7.4.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.5 Event router The event router combines various internal signals, interrupts, and the external interrupt ...
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... NXP Semiconductors 7.8.1 ISP (In-System Programming) mode In-System Programming (ISP) is programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. ISP can be used when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM ...
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... NXP Semiconductors Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC bit 3 bit 2 USB1 0 1 SPI (SSP USART3 1 0 [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Table 5. Boot mode ...
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... NXP Semiconductors 7.10 Memory mapping 0x2000 0000 16 MB static external memory CS3 0x1F00 0000 16 MB static external memory CS2 0x1E00 0000 16 MB static external memory CS1 0x1D00 0000 16 MB static external memory CS0 0x1C00 0000 reserved 0x1800 0000 64 MB SPIFI data 0x1400 0000 ...
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LPC1850/30/20/10 0x400F 0000 reserved 0x400E 5000 APB3 ADC1 0x400E 4000 peripherals ADC0 0x400E 3000 C_CAN0 0x400E 2000 DAC 0x400E 1000 I2C1 0x400E 0000 0x400C 8000 GIMA 0x400C 7000 QEI 0x400C 6000 APB2 ...
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... NXP Semiconductors 7.11 Decryption features 7.11.1 AES decryption The hardware AES decryption can decode data using the AES algorithm in conjunction with a 128-bit key. 7.11.1.1 Features • Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI). • Secure storage of keys. • Support for CMAC hash calculation to authenticate encrypted data. ...
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... NXP Semiconductors • Two GPIO group interrupts can be triggered by any pin or pins in each port. 7.13 AHB peripherals 7.13.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers ...
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... NXP Semiconductors example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.13.2.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. ...
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... NXP Semiconductors commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.13.3.1 Features • Interfaces to serial flash memory in the main memory map. • Supports classic and 4-bit bidirectional serial protocols. ...
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... NXP Semiconductors • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with data bits per device. ...
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... NXP Semiconductors The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024 768 pixels ...
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... NXP Semiconductors • Power management remote wake-up frame and magic packet detection • Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – ...
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... NXP Semiconductors 7.14.2.1 Features • Maximum UART data bit rate of 8 MBit/s. • Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • ...
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... NXP Semiconductors 7.14.4.1 Features • standard I supports Fast mode plus with bit rates Mbit/s. • uses standard I/O pins with bit rates 400 kbit/s (Fast I • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. ...
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... NXP Semiconductors 7.14.6 C_CAN Remark: The LPC1850/30/20/10 contain two C_CAN controllers. Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of reliability ...
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... NXP Semiconductors – Toggle on match. – Do nothing on match. • two match registers can be used to generate timed DMA requests. 7.15.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down ...
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... NXP Semiconductors • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 7.15.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window ...
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... NXP Semiconductors 7.16.2 Digital-to-Analog Converter (DAC) 7.16.2.1 Features • 10-bit resolution • Monotonic by design (resistor string architecture) • Controllable conversion speed • Low power consumption 7.17 Peripherals in the RTC power domain 7.17.1 RTC The Real Time Clock (RTC set of counters for measuring time when system power is on, and optionally when it is off ...
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... NXP Semiconductors • Timer/USART inputs • Enabling the USB controllers In addition, the CREG block contains the part identification and part configuration information. 7.18.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. ...
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... NXP Semiconductors 7.18.7 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 10 MHz to 25 MHz. The input frequency is multiplied high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO ...
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... NXP Semiconductors VDDIO VSS VDDREG VBAT RTCX1 RTCX2 VDDA VSSA VPP USB0_VDDA3V3_DRIVER USB0_VDDA3V3 Fig 11. LPC1850/30/20/10 power domains The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V regulator supply voltage DD(REG)(3V3) (3 input/output supply DD(IO) voltage V analog supply voltage DDA(3V3) (3 battery supply voltage BAT V supply voltage (3.3 V) DD(3V3) V polyfuse programming ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • ambient temperature (C), amb • R th(j-a) • sum of internal and I/O power dissipation D The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V regulator supply voltage DD(REG)(3V3) (3 analog supply voltage DDA(3V3) (3 ...
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... NXP Semiconductors Table 8. Static characteristics …continued +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter RESET pin V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys Standard I/O pins - normal drive strength ...
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... NXP Semiconductors Table 8. Static characteristics …continued +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter I pull-up current pu R series resistance s I/O pins - high drive strength C input capacitance I I LOW-level input current V IL ...
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... NXP Semiconductors Table 8. Static characteristics …continued +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current ...
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... NXP Semiconductors Table 8. Static characteristics …continued +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit ...
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... NXP Semiconductors Table 8. Static characteristics …continued +85 C, unless otherwise specified. Applies to parts LPC1850/30/20/10 Rev ‘A’ only. amb Symbol Parameter V differential input voltage i(dif) [15] USB1 pins (USB1_DP/USB1_DM) I OFF-state output OZ current V bus supply voltage BUS V differential input ...
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... NXP Semiconductors 10.1 Power consumption Remark: All power consumption data in this section apply to Rev ‘A’ of the LPC1850/30/20/10 parts only. X (X) Conditions: T pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 12. Typical supply current versus regulator supply voltage V ...
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... NXP Semiconductors X (X) Conditions: V enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 14. Typical supply current versus temperature in sleep mode X (X) Conditions: V Fig 15. Typical supply current versus temperature in Deep-sleep mode LPC1850_30_20_10 Preliminary data sheet <tbd> 3.0 V; internal pull-up resistors disabled; system PLL enabled; IRC ...
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... NXP Semiconductors X (X) Conditions: V Fig 16. Typical supply current versus temperature in Power-down mode X (X) Conditions: V Fig 17. Typical supply current versus temperature in Deep power-down mode LPC1850_30_20_10 Preliminary data sheet <tbd> BAT DD(IO <tbd> ...
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... NXP Semiconductors 10.2 Electrical pin characteristics <tbd> Conditions DD(REG)(3V3) port pins. Fig 18. Typical HIGH-level output voltage V HIGH-level output source current I + (μA) -20 -40 -60 -80 Conditions 40 C correspond to minimum values. Fig 20. Typical pull-up current I ...
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... NXP Semiconductors 120 I pd (μ Conditions 40 C correspond to maximum values. Fig 21. Typical pull-down current I LPC1850_30_20_10 Preliminary data sheet T =25 °C -40 ° 3.3 V. Simulated values. Values C are typical values. Values at DD(IO)) versus input voltage V pd All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Wake-up times Table 9. amb Symbol Parameter t wake-up time from Sleep mode wake Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. [ 1/CCLK with CCLK = CPU clock frequency. cy(clk) 11 ...
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... NXP Semiconductors 11.3 Crystal oscillator Table 11. amb Symbol Low-frequency mode (1 MHz - 20 MHz) t jit(per) High-frequency mode (20 MHZ - 25 MHz) t jit(per) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors 11.4 IRC and RTC oscillators Table 12. amb Symbol f osc(RC) f i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Conditions: Frequency values are typical values. ...
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... NXP Semiconductors Table 13. Dynamic characteristic: I + amb DD(REG)(3V3) Symbol Parameter t HIGH period of the SCL clock HIGH t data hold time HD;DAT t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors 2 11.6 I S-bus interface Table 14. amb refer to I2S0 and I2S1 pins. Simulated values. Symbol common to input and output output t v(Q) input t su(D) t h(D) [1] Clock to the I PCLK = BASE_APB1_CLK / 12 S-bus specification. I2Sx_TX_SCK I2Sx_TX_SDA I2Sx_TX_WS Fig 25. I LPC1850_30_20_10 ...
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... NXP Semiconductors I2Sx_RX_SCK I2Sx_RX_SDA I2Sx_RX_WS Fig 26. I 11.7 USART interface Table 15. amb Symbol T cy(clk) output t v(Q) LPC1850_30_20_10 Preliminary data sheet T cy(clk S-bus timing (receive) Dynamic characteristics: USART interface 3.6 V; 2.7 V DD(REG)(3V3) Parameter Conditions clock cycle time ...
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... NXP Semiconductors 11.8 SSP interface Table 16. Dynamic characteristics: SSP pins in SPI mode 2 amb DD(REG)(3V3) Symbol Parameter Conditions T clock cycle time full-duplex mode cy(clk) when only transmitting SSP master t data set-up time in SPI mode DS t data hold time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 27. SSP master timing in SPI mode LPC1850_30_20_10 Preliminary data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID DATA VALID MOSI t DS DATA VALID DATA VALID MISO All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 28. SSP slave timing in SPI mode LPC1850_30_20_10 Preliminary data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t DS MOSI DATA VALID DATA VALID t v(Q) MISO DATA VALID DATA VALID All information provided in this document is subject to legal disclaimers. ...
Page 112
... NXP Semiconductors 11.9 External memory interface Table 17. Dynamic characteristics: Static external memory interface for EMC_Dn for all others 2 3.6 V; values guaranteed by design. DD(IO) [1] Symbol Parameter Read cycle parameters t CS LOW to address valid CSLAV time t CS LOW to OE LOW time ...
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... NXP Semiconductors Table 17. Dynamic characteristics: Static external memory interface for EMC_Dn for all others 2 3.6 V; values guaranteed by design. DD(IO) [1] Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t CS HIGH to end of write CSHEOW time t BLS HIGH to data invalid ...
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... NXP Semiconductors EMC_An EMC_CSn EMC_OE EMC_BLSn EMC_WE EMC_Dn Fig 30. External static memory read/write access ( LPC1850_30_20_10 Preliminary data sheet t t CSLAV OEHANV t CSLOEL t OELOEH t t CSLBLSL CSHOEH t CSHBLSH CSHEOR t h(D) t CSLSOR EOR SOR All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 18. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; C EMC_An for EMC_Dn DD(REG)(3V3) DD(IO) = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0. Symbol Parameter T clock cycle time cy(clk) Common to read and write cycles ...
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... NXP Semiconductors EMC_CLKn delay > 0 EMC_CLKn delay = 0 EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn EMC_D[31:0] write EMC_D[31:0] read; delay > 0 EMC_D[31:0] read; delay = 0 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK register ...
Page 117
... NXP Semiconductors 11.10 USB interface Table 20. Dynamic characteristics: USB0 and USB1 pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP ...
Page 118
... NXP Semiconductors Table 21. Static characteristics: USB0 PHY pins Symbol Parameter High-speed mode P power consumption cons I analog supply current (3.3 V) DDA(3V3) I digital supply current DDD Full-speed/low-speed mode P power consumption cons I analog supply current (3.3 V) DDA(3V3) I digital supply current DDD Suspend mode I analog supply current (3.3 V) ...
Page 119
... NXP Semiconductors Table 22. amb design. Symbol Parameter t set-up time su t hold time h MII mode f clock frequency clk clock duty cycle clk t set-up time su t hold time h f clock frequency clk clock duty cycle clk t set-up time su t hold time h Output drivers can drive a load ...
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... NXP Semiconductors 11.12 SD/MMC Table 23. amb Symbol Parameter f clock frequency clk t data input set-up su(D) time t data input hold time h(D) data output valid t d(QV) delay time t data output hold time on pins SD_CMD, SD_DATn h(Q) Fig 34. SD/MMC timing 11.13 LCD Table 24. amb Symbol Parameter ...
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... NXP Semiconductors 12. ADC/DAC electrical characteristics Table 25. ADC characteristics V over specified ranges; T DDA(3V3) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
Page 122
... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. ...
Page 123
... NXP Semiconductors R Fig 36. ADC interface to pins Table 26. DAC characteristics V over specified ranges; T DDA(3V3) amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L t settling time s [1] In the DAC CR register, bit BIAS = 0 (see the LPC18xx user manual). ...
Page 124
... NXP Semiconductors 13. Application information 13.1 LCD panel signal usage Table 27. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC18xx pin LCD function used LCD_VD[23: LCD_VD7 - - LCD_VD6 - - LCD_VD5 - - LCD_VD4 - - LCD_VD3 P4_2 UD[3] LCD_VD2 P4_3 UD[2] LCD_VD1 P4_4 UD[1] LCD_VD0 ...
Page 125
... NXP Semiconductors Table 28. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC18xx pin LCD function used LCD_VD2 P4_3 UD[2] LCD_VD1 P4_4 UD[1] LCD_VD0 P4_1 UD[0] LCD_LP P7_6 LCDLP LCD_ENAB/ P4_6 LCDENAB/ LCDM LCDM LCD_FP P4_5 LCDFP LCD_DCLK ...
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... NXP Semiconductors Table 29. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 pin mode) LPC18xx LCD pin used function LCD_VD0 - - LCD_LP P7_6 LCDLP LCD_ENAB P4_6 LCDENAB/ /LCDM LCDM LCD_FP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE LCD_PWR P7_7 LCDPWR GP_CLKIN ...
Page 127
... NXP Semiconductors Table 30. Fundamental oscillation frequency 12 MHz 16 MHz 20 MHz Table 31. Fundamental oscillation frequency 15 MHz 20 MHz Fig 37. Slave mode operation of the on-chip oscillator Fig 38. Oscillator modes with external crystal model used for C LPC1850_30_20_10 Preliminary data sheet Recommended values for C in oscillation mode (crystal and external ...
Page 128
... NXP Semiconductors 13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C crystal usage have a common ground plane. Also connect the external components to the ground plain ...
Page 129
... NXP Semiconductors 13.5 Reset pin configuration reset Fig 40. Reset pin configuration LPC1850_30_20_10 Preliminary data sheet V DD(IO GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 15 December 2011 LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller V DD(IO) V DD(IO) ESD PIN ESD V SS 002aag702 © ...
Page 130
... NXP Semiconductors 14. Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT ...
Page 131
... NXP Semiconductors TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 0.50 mm nom 1.06 0.35 0.71 0.45 min 0.95 0.30 0.65 0.40 OUTLINE VERSION ...
Page 132
... NXP Semiconductors LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 133
... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 9.1 mm 1.2 0.3 0.65 0.4 8.9 OUTLINE VERSION IEC ...
Page 134
... NXP Semiconductors LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 135
... NXP Semiconductors LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 136
... NXP Semiconductors 15. Soldering Footprint information for reflow soldering of LBGA256 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 1.00 0.450 0.450 0.600 17.500 17.500 Fig 47. Reflow soldering of the LBGA256 package LPC1850_30_20_10 ...
Page 137
... NXP Semiconductors Footprint information for reflow soldering of TFBGA180 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.400 0.400 0.550 12.575 12.575 Fig 48. Reflow soldering of the TFBGA180 package LPC1850_30_20_10 Preliminary data sheet ...
Page 138
... NXP Semiconductors Footprint information for reflow soldering of LQFP208 package solder land occupied area DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 49. Reflow soldering of the LQFP208 package LPC1850_30_20_10 Preliminary data sheet Hx Gx (0.125 (8× Generic footprint pattern ...
Page 139
... NXP Semiconductors Footprint information for reflow soldering of LQFP144 package solder land occupied area DIMENSIONS 0.500 0.560 23.300 23.300 20.300 20.300 Fig 50. Reflow soldering of the LQFP144 package LPC1850_30_20_10 Preliminary data sheet Hx Gx (0.125 (8× Generic footprint pattern ...
Page 140
... NXP Semiconductors Footprint information for reflow soldering of TFBGA100 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.330 0.400 0.480 9.400 Fig 51. Reflow soldering of the TFBGA100 package LPC1850_30_20_10 Preliminary data sheet ...
Page 141
... NXP Semiconductors Footprint information for reflow soldering of LQFP100 package solder land occupied area DIMENSIONS 0.500 0.560 17.300 17.300 14.300 14.300 Fig 52. Reflow soldering of the LQFP100 package LPC1850_30_20_10 Preliminary data sheet Hx Gx (0.125 (8× Generic footprint pattern ...
Page 142
... NXP Semiconductors 16. Appendix 16.1 Static characteristics for LPC1850/30/20/10 Rev’-’ parts Table 32. Static characteristics +85 C, unless otherwise specified. Applies to LPC1850/30/20/10 Rev ‘-’ only. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V regulator supply voltage DD(REG)(3V3) (3 ...
Page 143
... NXP Semiconductors Table 32. Static characteristics …continued +85 C, unless otherwise specified. Applies to LPC1850/30/20/10 Rev ‘-’ only. amb Symbol Parameter Digital pins - RESET pin V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys Digital pins I LOW-level input current V ...
Page 144
... NXP Semiconductors Table 32. Static characteristics …continued +85 C, unless otherwise specified. Applies to LPC1850/30/20/10 Rev ‘-’ only. amb Symbol Parameter V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI Oscillator pins input voltage on pin V i(XTAL1) XTAL1 V output voltage on pin ...
Page 145
... NXP Semiconductors 60 I DD(REG)(3V3) (mA Conditions: T pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 53. Typical supply current versus regulator supply voltage V mode 60 I DD(REG)(3V3) (mA Conditions: V internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled ...
Page 146
... NXP Semiconductors X (X) Conditions: V enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 55. Typical supply current versus temperature in sleep mode 400 I DD(REG)(3V3) (μA) 300 200 100 Conditions: V Fig 56. Typical supply current versus temperature in Deep-sleep mode LPC1850_30_20_10 Preliminary data sheet ...
Page 147
... NXP Semiconductors 60 I DD(REG)(3V3) (μ Conditions: V Fig 57. Typical supply current versus temperature in Power-down mode 10.0 I DD(REG)(3V3) (μA) 8.0 6.0 4.0 2.0 Conditions: V Fig 58. Typical supply current versus temperature in Deep power-down mode LPC1850_30_20_10 Preliminary data sheet V DD(REG)(3V3) = 3.6 V 3.0 V 2 -40 - PD0_SLEEP0_MODE = 0x003F FCBA. ...
Page 148
... NXP Semiconductors Table 33. amb Peripheral IRC ADC DAC I2C0 I2C1 I2S SSP0 SSP1 USART0 UART1 USART2 USART3 USB0 USB1 Ethernet Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. 17. Abbreviations Table 34. Acronym ADC ...
Page 149
... NXP Semiconductors Table 34. Acronym JTAG LCD LSB LQFP MAC MCU MIIM n.c. OTG PHY PLL PWM RMII SDRAM SPI SSI SSP TCP/IP TTL UART ULPI USART USB UTMI LPC1850_30_20_10 Preliminary data sheet Abbreviations …continued Description Joint Test Action Group Liquid Crystal Display ...
Page 150
... NXP Semiconductors 18. Revision history Table 35. Revision history Document ID Release date Data sheet status LPC1850_30_20_10 v.3.1 20111215 • • LPC1850_30_20_10 v.3 20111206 • Modifications: • • • • • • • • • • • • • • • • • • • • ...
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... NXP Semiconductors Table 35. Revision history …continued Document ID Release date Data sheet status • Modifications: LPC1850_30_20_10 v.2.2 20110909 • Modifications: LPC1850_30_20_10 v.2.1 20110822 • Modifications: • • • • • LPC1850_30_20_10 Preliminary data sheet Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10: – LQFP208 pin configuration added. ...
Page 152
... NXP Semiconductors Table 35. Revision history …continued Document ID Release date Data sheet status LPC1850_30_20_10 v.2 20110713 • Modifications: • • • • • • • • • • • • • • • LPC1850_30_20_10 Preliminary data sheet Objective data sheet Power consumption data added (Figure 12 to Figure 17). ...
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... NXP Semiconductors Table 35. Revision history …continued Document ID Release date Data sheet status LPC1850_30_20_10 v.1.2 20110217 • Modifications: • • • • • • • • LPC1850_30_20_10 v.1 20110103 LPC1850_30_20_10 Preliminary data sheet Objective data sheet RMII removed from description of pin functions ENET_RXD2, ENET_RXD3, ENET_ER ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC1850_30_20_10 Preliminary data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 67 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 67 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 67 7.3 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 68 7.4 Nested Vectored Interrupt Controller (NVIC ...
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... NXP Semiconductors 9 Thermal characteristics . . . . . . . . . . . . . . . . . 91 10 Static characteristics 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 98 10.2 Electrical pin characteristics . . . . . . . . . . . . . 101 11 Dynamic characteristics . . . . . . . . . . . . . . . . 103 11.1 Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 103 11.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . 103 11.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 104 11.4 IRC and RTC oscillators . . . . . . . . . . . . . . . . 105 2 11.5 I C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2 11.6 I S-bus interface . . . . . . . . . . . . . . . . . . . . . . 107 11.7 USART interface 108 11.8 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 109 11 ...