LPC2361_62 NXP Semiconductors, LPC2361_62 Datasheet

The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 128 kB of embedded high-speed flash memory

LPC2361_62

Manufacturer Part Number
LPC2361_62
Description
The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 128 kB of embedded high-speed flash memory
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features and benefits
The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with up to 128 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2361/2362 are ideal for multi-purpose serial communication applications. They
incorporate a 10/100 Ethernet Media Access Controller (MAC) (LPC2362 only), USB full
speed device with 4 kB of endpoint RAM, four UARTs, two CAN channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I
This blend of serial communications interfaces combined with an on-chip 4 MHz internal
oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet (available as general purpose
SRAM for the LPC2361), 8 kB SRAM for USB and general purpose use, together with
2 kB battery powered SRAM make these devices very well suited for communication
gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit
DAC, one PWM unit, a CAN control unit, and up to 70 fast GPIO lines with up to 12 edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable
for industrial control and medical systems.
LPC2361/2362
Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP,
Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
Rev. 5 — 25 October 2011
ARM7TDMI-S processor, running at up to 72 MHz.
Up to 128 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
8 kB (LPC2361) or 32 kB (LPC2362) of SRAM on the ARM local bus for high
performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB SRAM for general purpose DMA use; also accessible by the USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA (LPC2362 only), USB DMA, and program execution from on-chip flash
with no contention between those functions. A bus bridge allows the Ethernet DMA to
access the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
2
S port, as well as for memory-to-memory transfers.
2
C interfaces, and an I
Product data sheet
2
S interface.

Related parts for LPC2361_62

LPC2361_62 Summary of contents

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LPC2361/2362 Single-chip 16-bit/32-bit MCU 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 5 — 25 October 2011 1. General description The LPC2361/2362 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time ...

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... MHz internal RC oscillator trimmed accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run. LPC2361_62 Product data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins). ...

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... LPC2362FBD100 128 32 16 [1] Available as general purpose SRAM for the LPC2361. LPC2361_62 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm Ethernet USB device + ...

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... D/A CONVERTER VBAT 2 kB BATTERY RAM power domain 2 power domain 2 RTCX1 RTC RTCX2 OSCILLATOR WATCHDOG TIMER SYSTEM CONTROL (1) LPC2362 only. Fig 1. LPC2361/2362 block diagram LPC2361_62 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64/128 kB 8/32 kB TEST/DEBUG FLASH SRAM INTERFACE ...

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... SCL1 [1] P0[2]/TXD0 98 [1] P0[3]/RXD0 99 [1] P0[4]/I2SRX_CLK/ 81 RD2/CAP2[0] LPC2361_62 Product data sheet 1 LPC2361FBD100 LPC2362FBD100 25 LPC2361/2362 pinning Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block ...

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... SCL2/MAT3[1] [1] P0[15]/TXD1/ 62 SCK0/SCK [1] P0[16]/RXD1/ 63 SSEL0/SSEL LPC2361_62 Product data sheet Type Description I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select driven by the master and received by the slave. Corresponds to the signal WS in the I O TD2 — CAN2 transmitter output. ...

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... CAP3[1] [2] P0[25]/AD0[2]/ 7 I2SRX_SDA/ TXD3 [3] P0[26]/AD0[3]/ 6 AOUT/RXD3 [4] P0[27]/SDA0 25 LPC2361_62 Product data sheet Type Description I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. I/O P0[18] — General purpose digital input/output pin. ...

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... P1[17]/ENET_MDIO 86 [1] P1[18]/ 32 USB_UP_LED/ PWM1[1]/CAP1[0] [1] P1[19]/ 33 USB_TX_E1/ USB_PPWR1/ CAP1[1] LPC2361_62 Product data sheet Type Description I/O P0[28] — General purpose digital input/output pin. Output is open-drain. 2 I/O SCL0 — clock input/output. Open-drain output (for I I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. ...

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... USB_INT1/ USB_OVRCR1/ CAP0[1] [1] P1[28]/USB_SCL1/ 44 PCAP1[0]/MAT0[0] [1] P1[29]/USB_SDA1/ 45 PCAP1[1]/MAT0[1] LPC2361_62 Product data sheet Type Description I/O P1[20] — General purpose digital input/output pin. O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. ...

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... P2[4]/PWM1[5]/ 69 DSR1/TRACESYNC [1] P2[5]/PWM1[6]/ 68 DTR1/TRACEPKT0 [1] P2[6]/PCAP1[0]/RI1/ 67 TRACEPKT1 LPC2361_62 Product data sheet Type Description I/O P1[30] — General purpose digital input/output pin — Monitors the presence of USB bus power. BUS Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. ...

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... P2[13]/EINT3/ 50 I2STX_SDA P3[0] to P3[31] [1] P3[25]/MAT0[0]/ 27 PWM1[2] [1] P3[26]/MAT0[1]/ 26 PWM1[3] P4[0] to P4[31] LPC2361_62 Product data sheet Type Description I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. O RTS1 — Request to Send output for UART1. O TRACEPKT2 — Trace Packet, bit 2. I/O P2[8] — General purpose digital input/output pin. ...

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... V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled. LPC2361_62 Product data sheet Type Description I/O P4[28] — ...

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... AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated address space within the APB address space. LPC2361_62 Product data sheet 2 C-bus 400 kHz specification. This pad requires an external pull-up to provide ...

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... USB device can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. ...

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... The LPC2361/2362 memory map incorporates several distinct regions as shown in Figure 3. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see 3.75 GB Fig 3. LPC2361_62 Product data sheet 4.0 GB AHB PERIPHERALS APB PERIPHERALS 3.5 GB 3.0 GB RESERVED ADDRESS SPACE 2 ...

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... The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 ...

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... GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC2361/2362 use accelerated GPIO functions: LPC2361_62 Product data sheet 2 S interfaces. ...

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... Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. ...

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... Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 ...

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... The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 ...

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... DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive LPC2361_62 Product data sheet . i(VREF) . i(VREF) All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU © NXP B.V. 2011. All rights reserved. ...

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... Features • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU © ...

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... S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I transmit and receive channel, each of which can operate as either a master or a slave. LPC2361_62 Product data sheet 2 C compliant bus interface with open-drain pins. ...

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... Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU 2 S input and output) ...

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... All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU © ...

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... Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. LPC2361_62 Product data sheet  256  cy(WDCLK)  4. cy(WDCLK) All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range 256. This input division provides a wide range of output frequencies from the same input frequency. LPC2361_62 Product data sheet Section 7.23.2 for additional information ...

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... The LPC2361/2362 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the battery RAM. LPC2361_62 Product data sheet ramp (in the case of power-on), the type of crystal and its electrical DD(3V3) All information provided in this document is subject to legal disclaimers ...

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... If power is supplied to the LPC2361/2362 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 ...

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... When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. LPC2361_62 Product data sheet pin powers the on-chip DC-to-DC converter which in turn provides power to and V pins together ...

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... The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 8 kB SRAM primarily intended for use by the USB. LPC2361_62 Product data sheet pins falls below 2.65 V. This Reset prevents DD(DCDC)(3V3) All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

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... Embedded trace Since the LPC2361/2362 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It LPC2361_62 Product data sheet 1 ⁄ All information provided in this document is subject to legal disclaimers. ...

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... It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2361/2362 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. LPC2361_62 Product data sheet All information provided in this document is subject to legal disclaimers. ...

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... The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC specification (J-STD-033B.1) for further details. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC2361_62 Product data sheet [1] Conditions ...

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... LQFP100 ja JEDEC (4.5 in  4 in) 0 m/s 1 m/s 2.5 m/s Single-layer (4.5 in  3 in) 0 m/s 1 m/s 2.5 m/s jc jb LPC2361_62 Product data sheet      – = ambient temperature (C), = the package junction-to-ambient thermal resistance (C/W) = sum of internal and I/O power dissipation Conditions Thermal resistance value ( ...

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... BAT Standard port pins, RESET, RTCK I LOW-level input current HIGH-level input IH current I OFF-state output OZ current LPC2361_62 Product data sheet Conditions core and external rail [ 3.3 V; DD(DCDC)(3V3 C; code T amb while(1){} executed from flash; no peripherals enabled; PCLK = CCLK ...

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... Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 LPC2361_62 Product data sheet …continued Conditions (0.5V ) < V < DD(3V3) I (1.5V ); DD(3V3) < 125  pin configured to provide a digital function output active =  ...

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... Allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] Minimum condition for V = 4.5 V, maximum condition for V I [12 [13] Includes external resistors of 33   and D. LPC2361_62 Product data sheet …continued Conditions 0 V < V < 3 (D+)  (D) ...

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... NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 4. I (μA) Fig 5. LPC2361_62 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) ...

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... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 6. 10.2 Deep power-down mode I DD(IO) (μA) Fig 7. LPC2361_62 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 −  3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode ...

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... NXP Semiconductors I (μA) Fig 8. I DD(DCDC)dpd(3v3) Fig 9. LPC2361_62 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3 −40 − ...

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... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 10. Typical HIGH-level output voltage V (mA) Fig 11. Typical LOW-level output current I LPC2361_62 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions 3.3 V; standard port pins. DD(3V3 0.2 Conditions 3.3 V; standard port pins. ...

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... Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] [3] Bus capacitance C in pF, from 400 pF. b Fig 12. External clock timing (with an amplitude of at least V LPC2361_62 Product data sheet over specified ranges. DD(3V3) Conditions CCLK; 40 C to +85 C IRC; 40 C to +85 C ...

Page 44

... JR1 t receiver jitter for paired transitions JR2 t EOP width at receiver EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. LPC2361_62 Product data sheet  3.6 V. [1] DD(3V3) Conditions - - [1] over specified ranges. Conditions pin configured as output pin configured as output ,unless otherwise specified ...

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... Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 11.5 Timing T PERIOD differential data lines Fig 13. Differential data-to-EOP transition skew and EOP width LPC2361_62 Product data sheet = 3 3.6 V; all voltages are measured with respect to DD(3V3) Conditions powered; 100 cycles unpowered;  100 cycles ...

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... NXP Semiconductors shifting edges SCK MOSI MISO Fig 14. MISO line set-up time in SSP Master mode LPC2361_62 Product data sheet t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU sampling edges 002aad326 © NXP B.V. 2011. All rights reserved. ...

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... T ADC and the ideal transfer curve. See [8] See Figure 16. LPC2361_62 Product data sheet   +85 C, unless otherwise specified; ADC frequency 4.5 MHz. Conditions ) is the difference between the actual step width and the ideal step width. See ...

Page 48

... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 15. ADC characteristics LPC2361_62 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...

Page 49

... L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC2361_62 Product data sheet LPC23XX 20 kΩ SAMPLE   +85 C unless otherwise specified Conditions All information provided in this document is subject to legal disclaimers. ...

Page 50

... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC23XX Fig 17. LPC2361/2362 USB interface on a self-powered device LPC23XX Fig 18. LPC2361/2362 USB interface on a bus-powered device LPC2361_62 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ V BUS Ω USB_D Ω ...

Page 51

... RSTOUT LPC2361/62 USB_SCL1 USB_SDA1 EINTn USB_D+ USB_D− Fig 19. LPC2361/2362 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC2361/62 USB_PWRD1 USB_OVRCR1 USB_PPWR1 Fig 20. LPC2361/2362 USB host port configuration LPC2361_62 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED SUSPEND R4 ...

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... External components and models used in oscillation mode are shown in Table 15 and the capacitances C fundamental mode oscillation (the fundamental frequency is represented Capacitance C S not be larger than 7 pF. Parameters F manufacturer. LPC2361_62 Product data sheet Ω 33 Ω which attenuates the input voltage by a factor C g 22), with an amplitude between 200 mV (RMS) and 1000 mV (RMS) ...

Page 53

... Fundamental oscillation frequency F 1 MHz to 5 MHz 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz Table 16. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz LPC2361_62 Product data sheet LPC2xxx XTAL1 XTAL2 XTAL model used for C /C evaluation ...

Page 54

... Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. LPC2361_62 Product data sheet LPC2xxx RTCX1 ...

Page 55

... Fig 25. Standard I/O pin configuration with analog input LPC2361_62 Product data sheet shows the possible pin modes for standard I/O pins with analog input function: output enable output driver pull-down enable ...

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... NXP Semiconductors 14.6 Reset pin configuration Fig 26. Reset pin configuration LPC2361_62 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU ESD ESD V SS 002aaf274 © ...

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... UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT407-1 136E20 Fig 27. Package outline SOT407-1 (LQFP100) LPC2361_62 Product data sheet ...

Page 58

... PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2361_62 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel ...

Page 59

... All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU Change notice - . stg to 0.05V DD(3V3) DD(3V3) characteristics”. - min/max to 2500/+2500. ESD . DRV . BAT to V DD(3V3) DD(DCDC)(3V3 DDA i(VREF) Supersedes LPC2361_62 v.4 . LPC2361_62 v.3 . © NXP B.V. 2011. All rights reserved ...

Page 60

... Figure 6: removed figure note row “V 20080804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 October 2011 LPC2361/62 Single-chip 16-bit/32-bit MCU Change notice Supersedes - LPC2361_62 v.2 - LPC2361_62 v.1 = 1.8 V” © NXP B.V. 2011. All rights reserved ...

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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC2361_62 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...

Page 62

... NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2361_62 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 63

... SPI serial I/O controller 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 SSP serial I/O controller . . . . . . . . . . . . . . . . . 22 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 7.17 I C-bus serial I/O controllers 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 7.18 I S-bus serial I/O controllers 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LPC2361_62 Product data sheet 7.19 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.19.1 Features 7.20 Pulse width modulator . . . . . . . . . . . . . . . . . . 25 7.20.1 Features 7.21 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 26 7.21.1 Features 7.22 RTC and battery RAM . . . . . . . . . . . . . . . . . . 26 7.22.1 Features ...

Page 64

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 25 October 2011 Document identifier: LPC2361_62 ...

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