LPC2367FBD100 NXP Semiconductors, LPC2367FBD100 Datasheet
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LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 7 — 20 October 2011 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation ...
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... NXP Semiconductors Serial interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed device with on-chip PHY and associated DMA controller (LPC2364/66/68 only). Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. ...
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... LPC2364FBD100 LQFP100 LPC2364HBD100 LQFP100 LPC2364FET100 TFBGA100 LPC2365FBD100 LQFP100 LPC2366FBD100 LQFP100 LPC2367FBD100 LQFP100 LPC2368FBD100 LQFP100 LPC2368FET100 TFBGA100 LPC2364_65_66_67_68 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic thin fine-pitch ball grid array package ...
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... Ethernet GP/USB RTC bus buffers LPC2364FBD100 128 LPC2364HBD100 128 LPC2364FET100 128 LPC2365FBD100 256 LPC2366FBD100 256 LPC2367FBD100 512 LPC2368FBD100 512 LPC2368FET100 512 Ethernet USB SD/MMC GP DMA device + Total 4 kB FIFO 2 34 RMII yes ...
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... NXP Semiconductors 5. Block diagram LPC2364/65/66/67/68 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 70 PINS TOTAL ETHERNET RMII(8) MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 LEGACY GPI/O P0 PINS TOTAL 6 × ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. LPC2364_65_66_67_68 Product data sheet 1 LPC2364FBD100 LPC2365FBD100 LPC2366FBD100 LPC2367FBD100 LPC2368FBD100 25 LPC2364/65/66/67/68 pinning ball A1 LPC2364FET100/LPC2368FET100 index area LPC2364/68 pinning TFBGA100 package All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 October 2011 ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 TDO 2 5 P1[10]/ENET_RXD1 6 9 P0[7]/I2STX_CLK/ 10 SCK1/MAT2[1] Row B 1 TMS 2 5 P1[9]/ENET_RXD0 6 9 P2[0]/PWM1[1]/ 10 TXD1/TRACECLK Row C 1 TCK 2 5 P1[8]/ENET_CRS Row D 1 P0[24]/AD0[1]/ 2 I2SRX_WS/CAP3[1] 5 P1[0]/ENET_TXD0 6 9 P2[4]/PWM1[5]/ 10 DSR1/TRACESYNC ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 1 P1[30]/ BUS AD0[4] 5 P1[24]/PWM1[5]/ 6 MOSI0 DD(3V3) LPC2364_65_66_67_68 Product data sheet …continued Pin Symbol XTAL1 DD(DCDC)(3V3) P0[22]/RTS1/ 11 MCIDAT0/TD1 All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 October 2011 ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0 2 5 P1[22]/MAT1[ P2[13]/EINT3/ 10 MCIDAT3/I2STX_SDA Row K 1 P3[26]/MAT0[1]/ 2 PWM1[3] 5 P1[23]/PWM1[4]/ 6 MISO0 9 P0[11]/RXD2/ 10 SCL2/MAT3[1] LPC2364_65_66_67_68 Product data sheet …continued Pin Symbol P0[27]/SDA0 P2[10]/EINT0 DD(3V3) P1[26]/PWM1[6]/ 7 CAP0[0] ...
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... NXP Semiconductors 6.2 Pin description Table 4. Pin description Symbol Pin Ball P0[0] to P0[31] [1] [1] P0[0]/RD1/TXD3 SDA1 [1] [1] P0[1]/TD1/RXD3 SCL1 [1] P0[2]/TXD0 98 C4 [1] [1] P0[3]/RXD0 99 A2 [1] [1] P0[4 I2SRX_CLK/ RD2/CAP2[0] [1] P0[5 I2SRX_WS/ TD2/CAP2[1] [1] [1] P0[6 I2SRX_SDA/ SSEL1/MAT2[0] [1] [1] P0[7 I2STX_CLK/ SCK1/MAT2[1] [1] P0[8 I2STX_WS/ MISO1/MAT2[2] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[9]/ 76 A10 I2STX_SDA/ MOSI1/MAT2[3] [1] P0[10]/TXD2 SDA2/MAT3[0] [1] [1] P0[11]/RXD2 SCL2/MAT3[1] [1] P0[15]/TXD1/ 62 F10 SCK0/SCK [1] [1] P0[16]/RXD1 SSEL0/SSEL [1] [1] P0[17]/CTS1 MISO0/MISO [1] [1] P0[18]/DCD1 MOSI0/MOSI [1] P0[19]/DSR1/ 59 G10 MCICLK/SDA1 [1] P0[20]/DTR1 MCICMD/SCL1 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[21]/RI1 MCIPWR/RD1 [1] P0[22]/RTS1/ 56 H10 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2 I2SRX_SDA/ TXD3 [3] P0[26]/AD0[3 AOUT/RXD3 [4] [4] P0[27]/SDA0 25 J2 [4] [4] P0[28]/SCL0 24 J1 [5] [5] P0[29]/USB_D [5] P0[30]/USB_D ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[0 ENET_TXD0 [1] [1] P1[1 ENET_TXD1 [1] [1] P1[4 ENET_TX_EN [1] P1[8 ENET_CRS [1] [1] P1[9 ENET_RXD0 [1] [1] P1[10 ENET_RXD1 [1] P1[14 ENET_RX_ER [1] P1[15 ENET_REF_CLK [1] [1] P1[16 ENET_MDC [1] [1] P1[17 ENET_MDIO [1] P1[18 USB_UP_LED/ PWM1[1]/ CAP1[0] [1] [1] P1[19]/CAP1[1] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[23]/PWM1[4 MISO0 [1] P1[24]/PWM1[5 MOSI0 [1] P1[25]/MAT1[ [1] [1] P1[26]/PWM1[6 CAP0[0] [1] [1] P1[27]/CAP0[ [1] [1] P1[28 PCAP1[0]/ MAT0[0] [1] P1[29 PCAP1[1]/ MAT0[1] [2] P1[30]/ BUS AD0[4] [2] [2] P1[31]/SCK1 AD0[5] P2[0] to P2[31] [1] [1] P2[0]/PWM1[1]/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[3]/PWM1[4 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5 DSR1/ TRACESYNC [1] P2[5]/PWM1[6]/ 68 D10 DTR1/ TRACEPKT0 [1] [1] P2[6]/PCAP1[0 RI1/ TRACEPKT1 [1] [1] P2[7]/RD2 RTS1/ TRACEPKT2 [1] P2[8]/TD2/ 65 E10 TXD2/ TRACEPKT3 [1] [1] P2[9 USB_CONNECT/ RXD2/EXTIN0 [6] P2[10]/EINT0 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] P2[12]/EINT2/ 51 K10 MCIDAT2/ I2STX_WS [6] [6] P2[13]/EINT3 MCIDAT3/ I2STX_SDA P3[0] to P3[31] [1] P3[25]/MAT0[0 PWM1[2] [1] [1] P3[26]/MAT0[1 PWM1[3] P4[0] to P4[31] [1] P4[28]/MAT2[0 TXD3 [1] [1] P4[29]/MAT2[1 RXD3 DBGEN - D4 [1][7] [1][7] TDO 1 A1 [1][8] TDI 2 C3 [1][8] [1][8] TMS 3 B1 ...
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... O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2364/65/66/67/68 being in Reset state. Note: This pin is available in LPC2364FBD100, LPC2365FBD100, LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only (LQFP100 package). I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... NXP Semiconductors [12] If the RTC is not used, these pins can be left floating. [13] Pad provides special analog functionality. [14] Pad provides special analog functionality. [15] Pad provides special analog functionality. [16] Pad provides special analog functionality. [17] Pad provides special analog functionality. 7. Functional description 7.1 Architectural overview ...
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... NXP Semiconductors The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM set • A 16-bit Thumb set The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’ ...
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... NXP Semiconductors 3.75 GB Fig 4. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...
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... NXP Semiconductors • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • ...
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... NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...
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... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...
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... NXP Semiconductors • Double buffer implementation for Bulk and Isochronous endpoints. 7.11 CAN controller and acceptance filters (LPC2364/66/68 only) The Controller Area Network (CAN serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. ...
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... NXP Semiconductors 7.13 10-bit DAC The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The maximum output value of the DAC is V 7.13.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive 7.14 UARTs The LPC2364/65/66/67/68 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface ...
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... NXP Semiconductors 7.16 SSP serial I/O controller The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master ...
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... NXP Semiconductors 7.18.1 Features • standard I • and I devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). ...
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... NXP Semiconductors 7.20 General purpose 32-bit timers/external event counters The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt ...
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... NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs ...
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... NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock ...
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... NXP Semiconductors 7.24.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy. Upon power-up or any chip reset, the LPC2364/65/66/67/68 uses the IRC as the clock source ...
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... NXP Semiconductors When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the ...
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... NXP Semiconductors On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. ...
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... NXP Semiconductors The first option assumes that power consumption is not a concern and the design ties the V DD(3V3) supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies ...
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... NXP Semiconductors 7.25.3 Code security (Code Read Protection - CRP) This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... NXP Semiconductors 7.25.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts ...
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... NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.26.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug lightweight debug monitor that runs in the background while users debug their foreground application ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 6. Thermal characteristics = ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics +85 C for standard devices, amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...
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... NXP Semiconductors Table 8. Static characteristics +85 C for standard devices, amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output ...
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... NXP Semiconductors Table 8. Static characteristics +85 C for standard devices, amb Symbol Parameter USB pins (LPC2364/66/68 only) I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold ...
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... NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2364_65_66_67_68 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) ...
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... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 10.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2364_65_66_67_68 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode ...
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... NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2364_65_66_67_68 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3) ...
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... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 11. Typical HIGH-level output voltage V (mA) Fig 12. Typical LOW-level output current I LPC2364_65_66_67_68 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions 3.3 V; standard port pins. DD(3V3 0.2 Conditions 3.3 V; standard port pins. ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics +85 C for standard devices, amb [1] over specified ranges. Symbol Parameter ARM processor clock frequency f operating frequency oper External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time ...
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... NXP Semiconductors 11.1 Internal oscillators Table 10. Dynamic characteristic: internal oscillators = 40 C to +85 C; 3.0 V amb Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 11.4 Flash memory Table 13. Dynamic characteristics of flash +85 C for standard devices, amb 3.6 V; all voltages are measured with respect to ground. DD(3V3) Symbol Parameter N endurance endu t retention time ret t erase time er t programming time prog [1] Number of program/erase cycles ...
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... NXP Semiconductors 11.5 Timing T PERIOD differential data lines Fig 14. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 15. MISO line set-up time in SSP Master mode LPC2364_65_66_67_68 Product data sheet crossover point crossover point differential data to SE0/EOP skew n × ...
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... NXP Semiconductors 12. ADC electrical characteristics Table 14. ADC characteristics 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors AD0[y] Fig 17. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin LPC2364_65_66_67_68 Product data sheet LPC23XX 20 kΩ SAMPLE All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 October 2011 LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers R vsi AD0[y] V EXT 002aac610 © ...
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... NXP Semiconductors 13. DAC electrical characteristics Table 15. DAC electrical characteristics 3 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L 14. Application information 14.1 Suggested USB interface solutions (LPC2364/66/68 only) LPC23XX Fig 18 ...
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... NXP Semiconductors LPC23XX Fig 19. LPC2364/66/68 USB interface on a bus-powered device 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors Fig 21. Oscillator modes and models: oscillation mode of operation and external crystal Table 16. Fundamental oscillation frequency F 1 MHz to 5 MHz 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz Table 17. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz ...
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... NXP Semiconductors 14.3 RTC 32 kHz oscillator component selection Fig 22. RTC oscillator modes and models: oscillation mode of operation and external The RTC external oscillator circuit is shown in integrated on chip, only a crystal, the capacitances C externally to the microcontroller. Table 18 capacitance of the crystal and is usually specified by the crystal manufacturer. The actual C influences oscillation frequency ...
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... NXP Semiconductors 14.5 Standard I/O pin configuration Figure 23 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Analog input (for ADC input channels) The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. ...
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... NXP Semiconductors 14.6 Reset pin configuration Fig 24. Reset pin configuration LPC2364_65_66_67_68 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 7 — 20 October 2011 LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers ESD ESD V SS 002aaf274 © ...
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... NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.65 0.4 OUTLINE VERSION IEC SOT926 Fig 26 ...
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... NXP Semiconductors 16. Abbreviations Table 19. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII MIIM PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2364_65_66_67_68 Product data sheet Abbreviations Description Analog-to-Digital Converter ...
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... NXP Semiconductors 17. Revision history Table 20. Revision history Document ID LPC2364_65_66_67_68 v.7 Modifications: LPC2364_65_66_67_68 Product data sheet Release date Data sheet status 20111020 Product data sheet • Table 13 “Dynamic characteristics of • Table 4 “Pin description”: Updated description for USB_UP_LED. • Table 4 “Pin description”: Added be left floating.” ...
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... NXP Semiconductors Table 20. Revision history …continued Document ID LPC2364_65_66_67_68 v.6 Modifications: LPC2364_65_66_67_68 v.5 Modifications: LPC2364_65_66_67_68 v.4 LPC2364_66_68 v.3 LPC2364_66_68 v.2 LPC2364_66_68 v.1 LPC2364_65_66_67_68 Product data sheet Release date Data sheet status 20100201 Product data sheet • Table 5 “Limiting values”: Changed V • Table 6: Updated min, typical and max values for oscillator pins. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC2364_65_66_67_68 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 18 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 18 7.2 On-chip flash programming memory . . . . . . . 19 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 Memory map 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 7.5.1 Interrupt sources ...
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... NXP Semiconductors 14.1 Suggested USB interface solutions (LPC2364/66/68 only 14.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.3 RTC 32 kHz oscillator component selection . . 58 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 58 14.5 Standard I/O pin configuration . . . . . . . . . . . . 59 14.6 Reset pin configuration . . . . . . . . . . . . . . . . . . 60 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17 Revision history ...