LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 60
LPC2420_60
Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2420_60.pdf
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Table 14.
C
[1]
[2]
[3]
[4]
[5]
[6]
Symbol
t
t
t
WEHDNV
BLSHANV
BLSHDNV
L
= 30 pF, T
V
V
T
Latest of address valid, CS LOW, OE LOW to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
Byte lane state bit (PB) = 1.
cy(CCLK)
OH
IH
= 2.5 V, V
= 2.5 V, V
Parameter
WE HIGH to data invalid
time
BLS HIGH to address
invalid time
BLS HIGH to data invalid
time
Dynamic characteristics: Static external memory interface
=
amb
1
⁄
CCLK
IL
=
OL
= 0.5 V.
.
= 0.2 V.
40
C to 85
C, V
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3]
[3]
[3]
= 3.0 V to 3.6 V.
Min
0.78 + T
0.29
0
cy(CCLK)
…continued
Typ
2.54 + T
0.20
2.54
cy(CCLK)
5.37
Max
5.96 + T
2.54
cy(CCLK)
Unit
ns
ns
ns
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