LPC2420_60

Manufacturer Part NumberLPC2420_60
DescriptionNXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
ManufacturerNXP Semiconductors
LPC2420_60 datasheet
 


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NXP Semiconductors
Table 16.
Dynamic characteristics: Dynamic external memory interface
C
= 30 pF, T
=
40
C to 85
L
amb
T
= 1/CCLK
cy(CCLK)
Symbol
Parameter
Common
t
chip select valid delay
d(SV)
time
t
chip select hold time
h(S)
t
row address strobe valid
d(RASV)
delay time
t
row address strobe hold
h(RAS)
time
t
column address strobe
d(CASV)
valid delay time
t
column address strobe
h(CAS)
hold time
t
write valid delay time
d(WV)
t
write hold time
h(W)
t
output enable valid delay
d(GV)
time
t
output enable hold time
h(G)
t
address valid delay time
d(AV)
t
address hold time
h(A)
Read cycle parameters
t
data input set-up time
su(D)
t
data input hold time
h(D)
Write cycle parameters
t
data output valid delay
d(QV)
time
t
data output hold time
h(Q)
[1]
See
Figure
18.
LPC2420_60
Product data sheet
C, V
= V
= 3.3 V, EMC Dynamic Read Config Register = 0x1 (RD = 01),
DD(DCDC)(3V3)
DD(3V3)
Conditions
Min
[1]
-
4 + T
[1]
[1]
-
3 + T
[1]
[1]
-
4 + T
[1]
[1]
-
4 + T
[1]
[1]
-
4 + T
[1]
[1]
-
4 + T
[1]
2.6 + T
[1]
2.6 + T
[1]
[1]
-
3.8 + T
[1]
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 22 September 2011
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
Typ
Max
3 + T
1.5 + T
cy(CCLK)
3 + T
-
cy(CCLK)
cy(CCLK)
3 + T
1.5 + T
cy(CCLK)
2.3 + T
-
cy(CCLK)
cy(CCLK)
3.4 + T
2.1 + T
cy(CCLK)
3 + T
-
cy(CCLK)
cy(CCLK)
3.4 + T
2.1 + T
cy(CCLK)
3 + T
-
cy(CCLK)
cy(CCLK)
3 + T
1.3 + T
cy(CCLK)
2.1 + T
-
cy(CCLK)
cy(CCLK)
2.6 + T
1.4 + T
cy(CCLK)
2.3 + T
-
cy(CCLK)
cy(CCLK)
1.5 + T
-
cy(CCLK)
cy(CCLK)
1.3 + T
-
cy(CCLK)
cy(CCLK)
2.6 + T
3 + T
cy(CCLK)
3.4 + T
-
cy(CCLK)
cy(CCLK)
© NXP B.V. 2011. All rights reserved.
Unit
ns
cy(CCLK)
ns
ns
cy(CCLK)
ns
ns
cy(CCLK)
ns
ns
cy(CCLK)
ns
ns
cy(CCLK)
ns
ns
cy(CCLK)
ns
ns
ns
ns
cy(CCLK)
ns
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