LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 64

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LPC2420_60

Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
LPC2420_60
Product data sheet
Fig 16. Differential data-to-EOP transition skew and EOP width
Fig 17. MISO line set-up time in SSP Master mode
T
PERIOD
differential
data lines
MOSI
MISO
shifting edges
SCK
Fig 18. Signal timing
n × T
differential data to
crossover point
SE0/EOP skew
PERIOD
output signal (O)
input signal (I)
All information provided in this document is subject to legal disclaimers.
+ t
reference
FDEOP
clock
Rev. 6.1 — 22 September 2011
t
su(SPI_MISO)
t
d(XXX)
crossover point
extended
Flashless 16-bit/32-bit microcontroller
t
su(D)
t
t
h(XXX)
h(D)
sampling edges
LPC2420/2460
source EOP width: t
receiver EOP width: t
002aad326
002aad636
© NXP B.V. 2011. All rights reserved.
FEOPT
002aab561
EOPR1
, t
EOPR2
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