LPC2468 NXP Semiconductors, LPC2468 Datasheet - Page 37

• Manufacturer Part Number: LPC2468
• Description: NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2468
Product data sheet
7.20.1 Features
7.21.1 Features
7.21 General purpose 32-bit timers/external event counters
The I
and one word select signal. The basic I
master, and one slave. The I
and receive channel, each of which can operate as either a master or a slave.
The LPC2468 includes four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
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The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
Configurable word select period in master mode (separately for I
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
All information provided in this document is subject to legal disclaimers.
Rev. 6.1 — 6 September 2011
2
S interface on the LPC2468 provides a separate transmit
2
S connection has one master, which is always the
Single-chip 16-bit/32-bit micro
2
S input and I
2
S input and output).
LPC2468
© NXP B.V. 2011. All rights reserved.
2
S output.
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