LPC2470 NXP Semiconductors, LPC2470 Datasheet - Page 46

• Manufacturer Part Number: LPC2470
• Description: NXP Semiconductors designed the LPC2470 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2470
Product data sheet
7.26.2 Boot process
7.26.3 Brownout detection
7.26.4 AHB
level, starts the wake-up timer (see description in
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, and a fixed number of clocks have passed.
Once the internal reset is removed, all of the processor and peripheral registers have
been initialized to predetermined values and the LPC2470 continues with booting from an
external static memory.
The processor always boots from the off-chip static memory bank 1, executing code from
address 0x8100 0000 (see
boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled,
and the external memory banks 0 and 1 are configured with the same data bus width. The
data bus width is determined by the setting of the two boot pins. Unused address pins are
configured as GPIO. See
address and data bus interface details.
Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.
The user code residing in the external boot memory must be linked to execute from
address location 0x8000 0000.
When booting from external memory, the interrupt vectors are mapped to the bottom of
the external memory. Once booting is over, the application must map interrupt vectors to
the proper domain.
The LPC2470 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if
this reset source is enabled in software) to inactivate the LPC2470 when the voltage on
the V
below 1 V, at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
The LPC2470 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB
SRAM.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
DD(DCDC)(3V3)
All information provided in this document is subject to legal disclaimers.
pins falls below 2.65 V. The BOD circuit maintains this reset down
Rev. 4 — 8 September 2011
Section 14.2 “Suggested boot memory interface solutions”
Table 5 “LPC2470 memory usage and
Flashless 16-bit/32-bit microcontroller
Section 7.25.3 “Wake-up
DD(DCDC)(3V3)
details”). During the
LPC2470
© NXP B.V. 2011. All rights reserved.
timer”),
pins. If this
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for