LPC2930 NXP Semiconductors, LPC2930 Datasheet

Page 1

... ARM9 flashless microcontroller with CAN, LIN, and USB Rev. 03 — 16 April 2010 1. General description The LPC2930 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 Host/OTG/Device controller, CAN and LIN SRAM, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, and communication markets ...

Page 2

... LQFP package. −40 °C to +85 °C ambient operating temperature range. LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

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... TCM All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB UART LIN 2.0/ CAN RS-485/ UART modem LPC2930 Version SOT459-1 Package LQFP208 © NXP B.V. 2010. All rights reserved ...

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... V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2930 block diagram LPC2930_3 Product data sheet JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ARM968E-S 1 master ...

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... Pin description 5.2.1 General description The LPC2930 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each, port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section ...

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... TIMER0 CAP3 PWM3 CAP1 PWM3 CAP2 - - - - TIMER0 MAT1 - TIMER0 MAT0 - PWM1 MAT2 PWM1 MAT3 PWM TRAP0 UART1 OUT1 PWM TRAP1 TIMER0 MAT2 LPC2930 Function 3 EXTBUS D21 LIN1/UART TXD LIN1/UART RXD TIMER0 MAT2 TIMER0 MAT3 EXTBUS D22 EXTBUS D23 - - - - EXTINT5 - EXTINT4 - USB_OVRCR1 ...

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... PWM TRAP3 USB_VBUS1 USB_CONNECT1 USB_SSPND1 USB_UP_LED1 TIMER1 CAP3, MSCSS PAUSE SPI0 SCS1 SPI0 SCS2 SPI0 SDO SPI0 SDI - SPI0 SCK - PWM TRAP3 - LPC2930 Function 3 - EXTINT7 - PWM3 MAT3 PWM3 MAT2 PWM3 MAT1 PWM3 MAT0 EXTBUS CS5 EXTBUS CS4 EXTBUS D7 EXTBUS D6 EXTBUS D5 EXTBUS D4 EXTBUS D3 ...

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... SPI0 SCS0 UART1 DCD UART0 DTR SPI0 SCS3 - SCL - SDA - PWM TRAP1 PWM TRAP0 SCL SDA EXTINT4 EXTINT5 LPC2930 Function 3 EXTBUS USB_PWRD1 - USB_LS1 - EXTBUS EXTBUS D0 - EXTBUS WE - EXTBUS OE - EXTBUS D10 EXTBUS D11 EXTBUS CS3 EXTBUS CS2 USB_SSPND1 QEI0 IDX © ...

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... LIN1 TXD/ UART TXD EXTBUS CS0 UART1 RXD UART1 TXD EXTINT2 PWM3 MAT5 PWM3 MAT4 EXTINT3 EXTINT6 EXTINT7 PWM0 MAT0 PWM0 MAT1 PWM3 MAT3 PWM3 MAT2 PWM3 MAT1 LPC2930 Function 3 EXTBUS D12 EXTBUS D13 EXTBUS CS1 EXTBUS A7 EXTBUS A6 EXTBUS D14 [3] (BOOT0) EXTBUS A5 EXTBUS A4 EXTBUS D15 [3] ...

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... CAN0 TXD - CAN0 RXD - PWM0 MAT0 - - PWM0 MAT1 - PWM2 MAT0 UART1 CTS PWM2 MAT1 UART0 DSR PWM0 MAT4 - PWM0 MAT5 UART1 RI PWM0 MAT2 LPC2930 Function 3 EXTBUS A0 SPI0 SCS0 SPI0 SCK EXTBUS D24 - EXTBUS D25 - EXTBUS D26 - - EXTBUS D27 - EXTBUS CS6 - EXTBUS CS7 - ...

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... LIN0 TXD/ UART TXD EXTBUS A20 LIN0 RXD/ UART TXD EXTBUS A21 PWM1 MAT0 PWM1 MAT1 PWM0 CAP0 PWM0 CAP1 PWM2 MAT2 - PWM2 MAT3 - PWM1 MAT2 - LPC2930 Function EXTBUS D29 - EXTBUS D30 EXTBUS D31 EXTBUS A8 EXTBUS A9 EXTBUS BLS0 EXTBUS BLS1 USB_SDA1 ...

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... UART0 TXD UART1 DTR UART0 OUT1 UART0 RXD - UART1 RTS PWM0 CAP2 PWM1 CAP0 PWM2 MAT0 PWM2 MAT1 PWM2 MAT4 PWM2 MAT5 PWM1 CAP1 PWM1 CAP2 PWM2 MAT2 LPC2930 Function 3 EXTBUS A11 - EXTBUS A12 - EXTBUS A13 - EXTBUS A22 - - EXTBUS A23 - - EXTBUS BLS2 ...

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... Bidirectional pad; analog port; plain input; 3-state output; slew rate control tolerant; TTL with hysteresis; programmable pull-up / pull-down / repeater. [2] USB pad. [3] For LPC2930 only, these are the boot control pins for configuring the external memory bus width. Use a weak pull-up/pull-down resistor (≈1 kΩ kΩ) to set level. See [4] Analog pad; Analog input/output. [5] Analog I/O pad ...

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... The ARM968E-S processor is described in detail in the ARM968E-S data sheet 6.3 On-chip static RAM In addition to the two 32 kB TCMs the LPC2930 includes two static RAM memories: one and one of 16 kB. Both may be used for code and/or data storage. In addition SRAM for the ETB can be used as static memory for code and data storage ...

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... ITCM/DTCM 0x0040 8000 memory 32 kB DTCM 0x0040 0000 reserved 0x0000 8000 32 kB ITCM 0x0000 0000 Fig 3. LPC2930 memory map 4 GB 0xFFFF FFFF PCR/VIC control 0xFFFF 8000 reserved 0xF080 0000 DMA interface to TCM 0xF000 0000 reserved 0xE018 3000 ETB control ...

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... LP_OSC speed is too low for the external debugging environment. 6.5.2 Reset strategy The LPC2930 contains a central module, the Reset Generator Unit (RGU) in the Power, Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards the peripheral modules. The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source ...

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... Clocking strategy 6.6.1 Clock architecture The LPC2930 contains several different internal clock areas. Peripherals like timers, SPI, UART, CAN and LIN have their own individual clock sources called base clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be unrelated in frequency and phase and can have different clock sources within the CGU ...

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... BASE_ICLK1_CLK BASE_IVNSS_CLK branch clocks BASE_PCR_CLK BASE_MSCSS_CLK CGU0 contains an overview of all the base blocks in the LPC2930 and their derived All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB BASE_USB_CLK branch clock BASE_USB_I2C_CLK ...

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... CLK_IVNSS_APB CLK_IVNSS_CANCA CLK_IVNSS_CANC0 CLK_IVNSS_CANC1 CLK_IVNSS_I2C0 CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 Parts of the device clocked Remark by this branch clock [1] watchdog timer ARM968E-S and TCMs AHB bus infrastructure AHB side of bridge in PCRSS [2] ...

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... Section 6.11 for details. Section 6.14 for details. All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 …continued Parts of the device clocked Remark by this branch clock APB side of the MSCSS timer 0 in the MSCSS timer 1 in the MSCSS ...

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... Base clock BASE_OUT_CLK BASE_USB_CLK BASE_USB_I2C_CLK 6.7 External Static Memory Controller (SMC) The LPC2930 contains an external Static Memory Controller (SMC) which provides an interface for external (off-chip) memory devices. Key features are: • Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and external I/O devices • ...

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... Do not drive any of the address lines as input even if they are not used. 6.7.3 Pin description The external static-memory controller module in the LPC2930 has the following pins, which are combined with other functions on the port pins of the LPC2930. the external memory controller pins. Table 12. ...

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... WSTOEN = 3, WST1 = 6 Reading from external memory All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB Figure WST1 002aae704 Figure 6. The relationship LPC2930 5. The relationship © NXP B.V. 2010. All rights reserved ...

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... WSTWEN = 3, WST2 = 7 to write enable (8 bit devices). Writing to external memory All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB WST2 002aae705 Figure 7. Extra wait states LPC2930 © NXP B.V. 2010. All rights reserved ...

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... WST1 WSTOEN WSTOEN = 2, WSTWEN = 4, WST1 = 6, WST2 = 4, IDCY = 5 Reading/writing external memory All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB WST2 WSTWEN IDCY LPC2930 002aae706 © NXP B.V. 2010. All rights reserved ...

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... The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host controller. The LPC2930 USB interface includes a device and OTG controller with on-chip PHY for device. The OTG switching protocol is supported through the use of an external controller. ...

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... When this function is not enabled BUS via its corresponding PINSEL register driven HIGH internally. positive differential data negative differential data All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 Interfacing - - - - - External OTG transceiver External OTG transceiver ...

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... System Control Unit (SCU) The system control unit contains system-related functions. The key feature is configuration of the I/O port-pins multiplexer. It defines the function of each I/O pin of the LPC2930. The I/O pin configuration should be consistent with peripheral function usage. The SCU has no external pins. 6.10.4 Event router The event router provides bus-controlled routing of input events to the vectored interrupt controller for use as interrupt or wake-up signals ...

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... The vectored interrupt-controller inputs are active HIGH. 6.10.4.1 Pin description The event router module in the LPC2930 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2930. pins connected to the event router. ...

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... CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. 6.11.3 Timer The LPC2930 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each timer has four capture inputs and/or match outputs ...

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... See section clocks. 6.11.3.1 Pin description The four timers in the peripheral subsystem of the LPC2930 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2930, see ...

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... FIFOs, but they can also be put into 450 mode without FIFOs. Remark: The LIN controller can be configured to provide two additional standard UART interfaces (see 6.11.4.1 Pin description The UART pins are combined with other functions on the port pins of the LPC2930. Table 16 Table 16. Symbol ...

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... The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. 6.11.5 Serial peripheral interface (SPI) The LPC2930 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: • ...

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... SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. 6.11.5.2 Pin description The SPI pins are combined with other functions on the port pins of the LPC2930, see Section Table 17. Symbol ...

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... Pin description The six GPIO ports in the LPC2930 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2930. pins. ...

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... Pin description The two CAN controllers in the LPC2930 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2930. pins (x runs from 0 to 1). ...

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... I2C SDA0/1 [1] Note that the pins are not I 6.13 Modulation and Sampling Control SubSystem (MSCSS) The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2930 includes four Pulse-Width Modulators (PWMs), three 10-bit successive approximation Analog-to-Digital Converters (ADCs) and two timers. LPC2930_3 Product data sheet ...

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... LPC2930_3 Product data sheet provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of 6.14.2. All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB LPC2930 © NXP B.V. 2010. All rights reserved ...

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... ARM9 microcontroller with CAN, LIN, and USB IDX0 PHA0 PHB0 ADC0 IN[7:0] ADC0 EXTSTART ADC1 IN[7:0] ADC1 EXTSTART ADC2 IN[7:0] ADC2 EXTSTART PWM0 MAT[5:0] PWM1 MAT[5:0] synch PWM2 MAT[5:0] PWM2 synch PWM3 PWM3 MAT[5:0] TRAP3 LPC2930 002aae256 © NXP B.V. 2010. All rights reserved ...

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... NXP Semiconductors 6.13.2 Pin description The pins of the LPC2930 MSCSS associated with the three ADC modules are described in Section Section Section Section 6.13.3 Clock description The MSCSS is clocked from a number of different sources: • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge. ...

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... ADC block diagram 6.13.4.2 Pin description The three ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2930. The VREFN and VREFP pins are common to all ADCs. LPC2930_3 Product data sheet Figure 9, shows the basic architecture of each ADC ...

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... The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB. Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 9. 6.13.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2930 includes four PWM modules with the following features. LPC2930_3 Product data sheet Analog to digital converter pins Pin name ...

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... This makes the PWM function as a motor drive. LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

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... A mechanism is included to synchronize the PWM period to other PWMs by providing a sync input and a sync output with programmable delay. Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 8 LPC2930. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2930_3 Product data sheet APB DOMAIN update ...

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... A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 6.13.5.4 Pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2930. pins. Table 23. Symbol ...

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... NXP Semiconductors 6.13.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2930. external pin. Table 24. Symbol MSCSS PAUSE 6.13.6.2 Clock description The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx ( 1), see Section power management ...

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... If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off. 6.14 Power, Clock and Reset Control SubSystem (PCRSS) The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2930 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). ...

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... FDIV[6:0] OUT7 OUT9 RGU RESET OUTPUT DELAY LOGIC INPUT DEGLITCH/ SYNC Section 6.6.2. CLK_SYS_PCRSS is derived from All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 PMU CGU1 OUT0 OUT1 OUT2 CLOCK GATES CLOCK ENABLE CONTROL PMU REGISTERS AHB_RST ...

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... Maximum frequency that guarantees stable operation of the LPC2930. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2930_3 Product data sheet CGU0 base clocks ...

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... Figure 12. All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB OUT 0 OUT 1 OUT 2 OUT 3 OUT 11 002aae147 LPC2930 BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_ICLK1_CLK © NXP B.V. 2010. All rights reserved ...

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... For every output generator generating the base clocks a LP_OSC EXTERNAL OSCILLATOR PLL Every secondary clock generator or output generator is Clocks that are inactive are automatically regarded as invalid, All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 FDIV0:6 clkout clkout120 clkout240 OUTPUT CONTROL clock outputs © ...

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... Figure . These clocks are either divided by 2 × the programmable post 2 All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 14. The input clock is fed directly to the Table 35, Dynamic characteristics. © NXP B.V. 2010. All rights reserved ...

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... Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When Power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal high once it has regained lock on the input clock. 6.14.2.3 Pin description The CGU0 module in the LPC2930 has the pins listed in Table 27. Symbol XOUT_OSC XIN_OSC ...

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... PLL clkout240 BASE_ICLK1_CLK Fig 15. Block diagram of the CGU1 6.14.3.1 Pin description The CGU1 module in the LPC2930 has the pins listed in Table 28. Symbol CLK_OUT 6.14.4 Reset Generation Unit (RGU) The RGU controls all internal resets. The key features of the Reset Generation Unit (RGU) are: • ...

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... MSCSS_TMR_RST I2C_RST QEI_RST DMA_RST USB_RST VIC_RST AHB_RST 6.14.4.2 Pin description The RGU module in the LPC2930 has the following pins. LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Reset output configuration Reset source power-on reset module POR_RST, RST pin RGU_RST, WATCHDOG PCR internal; source for COLD_RST ...

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... Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2930. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming ...

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... BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK BASE_MSCSS_CLK All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 Implemented switch on/off mechanism WAKE-UP AUTO RUN ...

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... CLK_TMR3 CLK_ADC0 CLK_ADC1 CLK_ADC2 CLK_USB_I2C CLK_USB 6.15 Vectored interrupt controller The LPC2930 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request. The key features are: • Level-active interrupt request with programmable polarity. • 56 interrupt request inputs. • ...

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... Software emulation of an interrupt-requesting device, including interrupts 6.15.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 6.6.2. © NXP B.V. 2010. All rights reserved ...

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... I/O port 2 pins 12 and 13; I/O port 3 pins 0 and 1. average value per input pin drive HIGH, output shorted to V SS(IO) drive LOW, output shorted to VDD(IO) All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 Min Max [1] - 1.5 −0.5 +2.0 −0.5 +2.0 −0.5 +4.6 −0.5 +6.0 − ...

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... ADC0 itself. The maximum input 3 . All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB Min Max −2000 [9] +2000 −500 +500 −750 +750 LPC2930 Unit © NXP B.V. 2010. All rights reserved ...

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... ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ Max 1.71 1.80 1. 475 2.7 - 3.6 - 0.5 3.25 1.71 1.80 1. 3.0 3.3 3.6 3.0 5.0 5 −0.5 [6][ 5.5 [ −0.5 - +3.6 −0 LPC2930 Unit V mA μA V μ μ μA mA μA V VREFP V V DD(IO) © NXP B.V. 2010. All rights reserved ...

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... ARM9 microcontroller with CAN, LIN, and USB = 3 5.5 V; DDA(ADC5V0) Min Typ Max 2 0.8 0 100 −25 −50 −115 [ −0 DD( 1.3 0 36.0 - 44.1 2 0.18 LPC2930 Unit μA μA μA μ DD(IO Ω © NXP B.V. 2010. All rights reserved ...

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... V to 5.5 V; DDA(ADC5V0) Min Typ Max 20.8 - 41.7 4.8 - 5.3 26.7 - 57.2 5 1.8 [ 160 - - 60 [ [10 [11] 1.1 1.4 1.6 [11] 1.0 1.3 1.5 [11] 50 120 180 . All clocks off. Analog modules powered down 1.5. × 1.5. LPC2930 Unit Ω Ω Ω °C on wafer amb © NXP B.V. 2010. All rights reserved ...

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... Product data sheet ARM9 microcontroller with CAN, LIN, and USB for 2 μs before reset is de-asserted; V must be above V DD(CORE) trip(high) All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 must be below DD(CORE) © NXP B.V. 2010. All rights reserved ...

Page 66

... T ADC and the ideal transfer curve. See [8] See Figure 16. ADC IN[y] Fig 16. Suggested ADC interface - LPC2930 ADC1/2 IN[y] pin LPC2930_3 Product data sheet − ° ° +85 C unless otherwise specified ...

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... D ). All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB (1) 1018 1019 1020 1021 1022 1023 LPC2930 offset gain error error 1024 002aae703 © NXP B.V. 2010. All rights reserved ...

Page 68

... V DD(CORE) All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB 90 core frequency (MHz) 1.8 core voltage (V) (active mode) DD(CORE) LPC2930 002aae241 130 002aae240 1.9 © NXP B.V. 2010. All rights reserved ...

Page 69

... V = 3.3 V. DD(IO) All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB 35 60 temperature (°C) 85 °C 25 °C 0 °C −40 °C 4.0 5.0 I LPC2930 002aae239 85 002aae689 6.0 (mA) OL © NXP B.V. 2010. All rights reserved ...

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... V. I All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB 85 °C 25 °C 0 °C −40 °C 3.0 4.0 5 3.6 V DD(IO) 3 temperature (°C) LPC2930 002aae690 6.0 I (mA) OH 002aae691 85 © NXP B.V. 2010. All rights reserved ...

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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB V = 2.7 V DD(IO) 3 temperature (°C) LPC2930 002aae692 85 © NXP B.V. 2010. All rights reserved ...

Page 72

... ARM9 microcontroller with CAN, LIN, and USB [1] Min Typ [ [ 0.4 0.5 [ [3] - 500 [ 156 - - - - - [3] - 0.4 LPC2930 Max Unit 13 MHz 125 MHz 100 ns 0.6 MHz μs - 100 MHz μ MHz 160 MHz 320 MHz 63 °C ambient amb © NXP B.V. 2010. All rights reserved ...

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... Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB 1.9 V 1 temperature (°C) LPC2930 002aae373 85 © NXP B.V. 2010. All rights reserved ...

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... ARM9 microcontroller with CAN, LIN, and USB Min Typ 8 1.3 - 160 - −2 - −18.5 - − extended source EOP width: t receiver EOP width: t LPC2930 Max Unit 13.8 ns 13.7 ns 109 % 2.0 V 175 +18 FEOPT , t EOPR1 EOPR2 002aab561 © NXP B.V. 2010. All rights reserved. ...

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... Min Typ 20 + 0.1 × 5.5 V; DDA(ADC5V0) Min Typ ⁄ 65024 clk(SPI) ⁄ 65024 clk(SPI LPC2930 Max Unit - °C ambient amb Max Unit ⁄ MHz 2 clk(SPI) ⁄ MHz 4 clk(SPI °C ambient amb sampling edges 002aae695 © ...

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... WSTOEN +1) × T CLCL 0 + WSTOEN × (WSTWEN + 0.5) × T WSTWEN × T CLCL (WSTWEN + 0.5) × T −0.1 (WST2 − WSTWEN +1) × T CLCL (WST2 − WSTWEN +2) × T CLCL = −0.5 × T CSHBLSH = t CSLBLSL CSLWEL LPC2930 Max Unit 100 ns 20 CLCL - ns CLCL ...

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... ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t CSLWEL t WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 t CSHOEH t h(D) 002aae687 t CSHBLSH t WELWEH 002aae688 © NXP B.V. 2010. All rights reserved ...

Page 78

... Duty cycle clock should be as close as possible 10. Application information 10.1 Operating frequency selection The LPC2930 is specified to operate at a maximum frequency of 125 MHz, maximum temperature of 85 °C, and maximum core voltage of 1.89 V. that the user can achieve higher operating frequencies for the LPC2930 by controlling the temperature and the core voltage accordingly ...

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... All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB 65 temperature (°C) 1.85 core voltage (V) LPC2930 002aae194 85 002aae193 1.95 © NXP B.V. 2010. All rights reserved ...

Page 80

... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2930 USB interface on a self-powered device LPC29xx Fig 33. LPC2930 USB interface on a bus-powered device LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ USB_VBUS Ω ...

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... USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 34. LPC2930 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) RESET_N ADR/PSW OE_N/INT_N V DD(IO) ...

Page 82

... USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 35. LPC2930 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω 33 Ω 15 kΩ 15 kΩ ...

Page 83

... USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC293X USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 USB_VBUS2 Fig 36. LPC2930 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) 33 Ω 33 Ω 15 kΩ 15 kΩ ...

Page 84

... SDOn MSB OUT SDIn MSB IN DATA VALID SDOn MSB OUT DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 DATA VALID LSB OUT DATA VALID LSB IN LSB OUT LSB IN DATA VALID LSB IN DATA VALID LSB OUT ...

Page 85

... A[22] A[23] CS7 OE WE BLS0 BLS0 BLS1 BLS1 BLS2 BLS2 BLS3 BLS3 IO[31:0] D[31:0] A[2] A[21] A[23] All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 8-bit MEMORY 002aae529 16-bit MEMORY A[0] 002aae530 32-bit MEMORY A[0] 002aae531 © NXP B.V. 2010. All rights reserved. ...

Page 86

... LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB LPC2930 boot configuration Port Function P4[10] OE P4[11] WE P4[17] CS7 P4[12] BLS0 P4[13] BLS1 P4[14] BLS2 P4[15] BLS3 P1[0] A0 P1[1] A1 P1[2] A2 P1[3] A3 P1[4] A4 P1[5] ...

Page 87

... C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C mode, a minimum of 200 mV manual UM10316. LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB LPC2930 boot configuration Port Function P1[21] D7 P5[0] D8 P5[1] D9 P5[2] ...

Page 88

... PCB layout. LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB LPC29xx XIN_OSC C i 100 pF All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 C g 002aae730 and C , and and C should be chosen x1 x2 © ...

Page 89

... Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION LPC2930 SOT459 θ θ 1. 1.08 0 ISSUE DATE 00-02-06 03-02-20 © NXP B.V. 2010. All rights reserved ...

Page 90

... Solder bath specifications, including temperature and impurities LPC2930_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

Page 91

... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 44. All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 Figure 44) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 92

... MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 ARM9 microcontroller with CAN, LIN, and USB peak temperature LPC2930 time 001aac844 © NXP B.V. 2010. All rights reserved ...

Page 93

... Pulse Width Modulator PHYsical layer Phase-Locked Loop Quadrature Encoder Interface Queued-SPI Reduced Instruction Set Computer System Control Unit SCU Function Select Port All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

Page 94

... Revision history Document ID Release date LPC2930_3 20100416 • Modification: Pin description for pins 187 (GPIO 4, pin 15) and 188 (GPIO 5, pin 15) corrected. • Table 41 “LPC2930 boot configuration” • USB logo added. • Document template updated. LPC2930_2 20100108 • Modifications Product status changed from Preliminary to Product • ...

Page 95

... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

Page 96

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 © NXP B.V. 2010. All rights reserved ...

Page 97

... Clock description . . . . . . . . . . . . . . . . . . . . . . 45 6.13.6 Timers in the MSCSS 6.13.6.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 46 6.13.6.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 46 6.13.7 Quadrature Encoder Interface (QEI 6.13.7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 47 6.13.7.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 47 All information provided in this document is subject to legal disclaimers. Rev. 03 — 16 April 2010 LPC2930 2 C-bus serial I/O controllers . . . . . . . . . . . . . 37 © NXP B.V. 2010. All rights reserved. continued >> ...

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... NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2930 Legal information . . . . . . . . . . . . . . . . . . . . . . 95 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 95 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Contact information . . . . . . . . . . . . . . . . . . . . 96 Contents Date of release: 16 April 2010 Document identifier: LPC2930_3 All rights reserved. ...