LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 15

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.3 JTAG
6.4 NAND flash controller
The Joint Test Action Group (JTAG) interface allows the incorporation of the
LPC3130/3131 in a JTAG scan chain.
This module has the following features:
The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An error
correction encoder/decoder (ECC enc/dec) module allows for hardware error correction
for support of Multi-Level Cell (MLC) NAND flash devices.
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects any errors.
This module has the following features:
Fig 4. Block diagram of the NAND flash controller
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ARM926 debug access
Boundary scan
Dedicated NAND flash interface with hardware controlled read and write accesses.
Wear leveling support with 516 byte mode.
Software controlled command and address transfers to support wide range of flash
devices.
shows a block diagram of the NAND flash controller module. The heart of the
Rev. 1 — 9 February 2009
AHB MULTILAYER MATRIX
NAND INTERFACE
CONTROLLER
Low-cost, low-power ARM926EJ-S microcontrollers
BUFFER
ENCODER/
DECODER
ECC
DMA transfer request
LPC3130/3131
002aae127
© NXP B.V. 2009. All rights reserved.
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