LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 20

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.12 Interrupt controller (INTC)
Table 9:
The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features:
Peripheral name
NAND flash controller
SPI
MCI
LCD interface
UART
I2C0/1-bus master/slave
I2S0/1 receive
I2S0/1 transmit
PCM interface
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– Data is transferred from incrementing memory to a fixed address of a peripheral.
Peripheral to memory:
– Data is transferred from a fixed address of a peripheral to incrementing memory.
Supports single data transfers for all transfer types.
Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
The DMA controller has 12 channels.
Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
Compatible with ARM flow control for single requests (sreq), last single requests
(lsreq), terminal count info (tc), and dma clearing (clr).
Supports swapping in endianess of the transported data.
The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM
core. The ARM core supports two distinct levels of priority on all interrupt sources,
FIQ for high priority interrupts and IRQ for normal priority interrupts.
Software interrupt request capability associated with each request input.
Visibility of the interrupt’s request state before masking.
Support for nesting of interrupt service routines.
Interrupts routed to IRQ and to FIQ are vectored.
The flow is controlled by the peripheral.
The flow is controlled by the peripheral.
Peripherals that support DMA access
Rev. 1 — 9 February 2009
Low-cost, low-power ARM926EJ-S microcontrollers
Supported Transfer Types
Memory to memory
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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