LPC3130_3131 NXP Semiconductors, LPC3130_3131 Datasheet - Page 29

• Manufacturer Part Number: LPC3130_3131
• Description: The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.23 Pulse Code Modulation (PCM) interface
6.24 LCD interface
The PCM interface supports the PCM and IOM interfaces.
The IOM (ISDN Oriented Modular) interface is primarily used to interconnect
telecommunications ICs providing ISDN compatibility. It delivers a symmetrical full-duplex
communication link containing user data, control/programming lines, and status channels.
PCM (Pulse Code Modulation) is a very common method used for transmitting analog
data in digital format. Most common applications of PCM are digital audio as in Audio CD
and computers, digital telephony and videos.
This module has the following features:
The dedicated LCD interface contains logic to interface to a 6800 (Motorola) or 8080
(Intel) compatible LCD controllers which support 4/8/16 bit modes. This module also
supports a serial interface mode. The speed of the interface can be adjusted in software
to match the speed of the connected LCD display.
This module has the following features:
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SIR-IrDA encoder/decoder (from 2400 to 115 kBd).
Supports maskable interrupts.
Supports DMA transfers.
Four-wire serial interface.
Can function in both Master and Slave modes.
Supports:
– PCM: Single clocking physical format.
– Multi-Protocol (MP) PCM: Configurable directional per slot.
– IOM-2: Extended ISDN-Oriented modular. Double clocking physical format.
Twelve eight bit slots in a frame with enabling control per slot.
Internal frame clock generation in master mode.
Receive and transmit DMA handshaking using a request/clear protocol.
Interrupt generation per frame.
4/8/16 bit parallel interface mode: 6800-series, 8080-series.
Serial interface mode.
Supports multiple frequencies for the 6800/8080 bus to support high- and low-speed
controllers.
Supports polling the busy flag from LCD controller to off-load the CPU from polling.
Contains an 16 byte FIFO for sending control and data information to the LCD
controller.
Supports maskable interrupts.
Supports DMA transfers.
Rev. 1 — 9 February 2009
Low-cost, low-power ARM926EJ-S microcontrollers
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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