EP4CGX150DF27I7N

Manufacturer Part NumberEP4CGX150DF27I7N
DescriptionIC CYCLONE IV FPGA 150K 672FBGA
ManufacturerAltera Corporation
SeriesCYCLONE® IV GX
EP4CGX150DF27I7N datasheets

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Specifications of EP4CGX150DF27I7N

Number Of Logic Elements/cells149760Number Of Labs/clbs9360
Total Ram Bits6635520Number Of I /o393
Number Of Gates-Voltage - Supply1.16 V ~ 1.24 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case672-BBGALead Free StatusLead free
Rohs StatusRoHS Compliant  
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1–38
I/O Timing
Use the following methods to determine I/O timing:
■
the Excel-based I/O Timing
■
the Quartus II timing analyzer
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
f
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
website.
Glossary
Table 1–46
lists the glossary for this chapter.
Table 1–46. Glossary (Part 1 of 5)
Letter
Term
A
—
B
—
C
—
D
—
E
—
F
f
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
HSCLK
GCLK
Input pin directly to Global Clock network.
G
GCLK PLL
Input pin to Global Clock network through the PLL.
H
HSIODR
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input Waveforms
for the SSTL
I
V
SWING
Differential I/O
Standard
Cyclone IV Device Handbook,
Volume 3
Chapter 1: Cyclone IV Device Datasheet
Cyclone IV Devices
Definitions
—
—
—
—
—
V
IH
V
REF
V
IL
November 2011 Altera Corporation
I/O Timing

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