EP3CLS70U484C8 Altera Corporation, EP3CLS70U484C8 Datasheet - Page 4

• Manufacturer Part Number: EP3CLS70U484C8
• Description: IC CYCLONE III FPGA 70K 484UBGA
• Manufacturer: Altera Corporation
• Series: Cyclone® IIIr

Specifications of EP3CLS70U484C8

• Number Of Logic Elements/cells: 70208
• Number Of Labs/clbs: 4388
• Total Ram Bits: 3068928
• Number Of I /o: 278
• Number Of Gates: -
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant


Features and benefits
You can turn ideas into revenue faster than
ever because we deliver numerous features and
benefits that help you lower your system and
development costs. Flexibility enables you to
keep up with fast-evolving standards easily.
Scalable digital signal processing (DSP) perfor-
mance and embedded memory let you increase
or enhance feature sets. All of this with the lowest
power consumption of any FPGA available
today. To top it off, we’re the lowest-cost FPGA
solution around. Choose Altera to win.
Cyclone III FPGAs • March 2007 • www.altera.com
best value
Cost optimized
system
Lowest-power
for the
65-nm
integration
anywhere
Complete
FPGAs
• Manufactured using a low-power 65-nm process technology.
• Core static power as low as 35 mW at 25
• Support for hot-socketing operation so unused I/O banks can be turned
• Low-power benefits include: system thermal management, elimination
• Staggered I/O ring to reduce die size and board space.
• Selection of low-cost packages.
• Support for low-cost serial flash and commodity parallel flash configu-
• Cyclone series FPGAs are built from the ground up for low cost.
• 1.7 times the density to 120,000 logic elements (LEs) and over 3.5 times
• 260-MHz multiplier performance with the highest multiplier-to-logic
• Robust clock management and synthesis with dynamically reconfigu-
• Improved signal integrity with adjustable I/O slew rates.
• Support for high-speed external memory interfaces including DDR,
• Support for I/O standards including LVTTL, LVCMOS, SSTL, High-
Cyclone III floorplan
off when there’s no current.
or reduction in cooling system costs, and extended battery life for
portable applications.
ration devices.
the embedded memory to 4 Mbits over Cyclone II FPGAs.
ratio in the industry.
rable and flexible phase-locked loops (PLLs).
DDR2, SDR SDRAM, and QDRII SRAM with an autocalibrating PHY
for fast timing closure.
Speed Transceiver Logic (HSTL), PCI Express, LVPECL, LVDS, mini-
LVDS, reduced swing differential signaling (RSDS), and point-to-point
differential signaling (PPDS).
Cyclone III floorplan
o
C junction temperature.
Phase-locked loops
M9K memory blocks
Logic array
Embedded 18-bit x 18-bit
multipliers
Side I/O cells with support for
LVDS signals up to 875 Mbps
Top and bottom I/O cells for
memory interfaces up to 400 Mbps