EP4SGX180FF35C4N Altera Corporation, EP4SGX180FF35C4N Datasheet

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EP4SGX180FF35C4N

Manufacturer Part Number
EP4SGX180FF35C4N
Description
IC STRATIX IV FPGA 180K 1152FBGA
Manufacturer
Altera Corporation
Series
Stratix® IV GXr
Datasheet

Specifications of EP4SGX180FF35C4N

Number Of Logic Elements/cells
175750
Number Of Labs/clbs
7030
Total Ram Bits
13954048
Number Of I /o
564
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant

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Stratix IV Device Handbook Volume 4: Device Datasheet
and Addendum
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIV5V4-5.2
Volume 4: Device Datasheet and Addendum
Stratix IV Device Handbook

Related parts for EP4SGX180FF35C4N

EP4SGX180FF35C4N Summary of contents

Page 1

Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Volume 4: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V4-5.2 Stratix IV Device Handbook ...

Page 2

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...

Page 3

... I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61 Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62 Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63 Chapter 2. Addendum to the Stratix IV Device Handbook Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 December 2011 Altera Corporation Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Contents ...

Page 4

... Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Contents December 2011 Altera Corporation ...

Page 5

... Chapter 1. DC and Switching Characteristics for Stratix IV Devices Revised: Part Number: SIV54001-5.2 Chapter 2. Addendum to the Stratix IV Device Handbook Revised: Part Number: SIV54002-1.5 December 2011 Altera Corporation December 2011 February 2011 Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter Revision Dates ...

Page 6

... Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter Revision Dates December 2011 Altera Corporation ...

Page 7

... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. December 2011 Altera Corporation Section I. Device Datasheet and Addendum for Stratix IV Devices Stratix IV Device Handbook Volume 1 ...

Page 8

... I–2 Stratix IV Device Handbook Volume 1 Section I: Device Datasheet and Addendum for Stratix IV Devices December 2011 Altera Corporation ...

Page 9

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...

Page 10

... Chapter 1: DC and Switching Characteristics for Stratix IV Devices Table 1–1, Table Description Description Electrical Characteristics 1–2, and Table 1–3 may cause Minimum Maximum Unit -0.5 1.35 V -0.5 1.8 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.9 V -0.5 3.75 V -0.5 1.35 V -0.5 3.75 V -0.5 4 -55 125 °C -65 150 °C Minimum Maximum Unit -0.5 3.75 V -0.5 3.75 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.35 V -0.5 1.8 V -0.5 1.8 V December 2011 Altera Corporation ...

Page 11

... Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. December 2011 Altera Corporation Description Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 1–3 ...

Page 12

... Core voltage and periphery circuitry power CC (Stratix IV GT) supply Power supply for programmable power V CCPT technology Auxiliary supply for the programmable V CCAUX power technology I/O pre-driver (3.0 V) power supply V (2) CCPD I/O pre-driver (2.5 V) power supply December 2011 Altera Corporation Description Condition (V) 4.0 4.05 4.1 4.15 4.2 4.25 AC input voltage 4.3 4.35 4.4 4.45 4.5 4.55 4.6 Table 1– ...

Page 13

... CCA_R V Transceiver HIP digital power (left side) CCHIP_L V Transceiver HIP digital power (right side) CCHIP_R V Receiver power (left side) CCR_L V Receiver power (right side) CCR_R December 2011 Altera Corporation Condition Minimum — — — — — — — — — — ...

Page 14

... DC Characteristics This section lists the supply current, I/O pin leakage current, bus hold, on-chip termination (OCT) tolerance, input pin capacitance, and hot socketing specifications. December 2011 Altera Corporation Description Minimum 1.045 1.045 1 ...

Page 15

... IN overdrive I ODL V CCIO current High 0V < V < IN overdrive I ODH V CCIO current Bus-hold V — TRIP trip point December 2011 Altera Corporation and the PowerPlay Power Analysis Description Conditions CCIOMAX CCIOMAX V CCIO 1.2 V 1.5 V 1.8 V Min Max Min Max Min 22.5 — ...

Page 16

... Internal series termination 25- without calibration (25- 3.0 and 2.5 setting) Internal series termination 25- without calibration (25- 1.8 and 1.5 setting) Internal series termination 25- without calibration (25- 1.2 setting) December 2011 Altera Corporation Table 1–10 (Note 1) Conditions V = 3.0, 2.5, 1.8, CCIO 1.5, 1 3.0, 2.5, 1.8, CCIO 1.5, 1 2.5, 1.8, 1.5, CCIO 1 3.0, 2.5, 1.8, CCIO 1 ...

Page 17

... V (5) dR/dT is the percentage change of R (6) dR/dV is the percentage change of R Table 1–12 lists the OCT variation after the power-up calibration. Table 1–12. OCT Variation after Power-Up Calibration Symbol dR/dV December 2011 Altera Corporation Conditions V = 3.0 and 2.5 V CCIO V = 1.8 and 1.5 V CCIO ...

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... The I/O ramp rate more. For ramp rates faster than 10 ns, |I capacitance and dv/dt is the slew rate. (2) These specifications are preliminary. December 2011 Altera Corporation Description OCT variation with temperature without re-calibration range of ±5% and temperature range of 0° to 85°C. ...

Page 19

... Table 1–17. Single-Ended I/O Standards (Part (V) CCIO I/O Standard Min Typ Max LVTTL 2.85 3 3.15 LVCMOS 2.85 3 3.15 December 2011 Altera Corporation Table 1–15 lists the hysteresis specifications across the supported Description Condition ( 3.3 CCIO V = 2.5 Hysteresis for Schmitt CCIO trigger input V = 1.8 CCIO V = 1.5 CCIO ...

Page 20

... I/O Standard Min Max SSTL REF -0.3 Class I 0.15 SSTL REF -0.3 Class II 0.15 SSTL- REF -0.3 Class I 0.125 SSTL- REF -0.3 Class II 0.125 SSTL- REF — Class I 0.1 December 2011 Altera Corporation V ( Min Max Min Max -0.3 0.7 1.7 3.6 0. CCIO -0 0.3 CCIO CCIO 0. CCIO -0 0.3 CCIO CCIO 0. CCIO -0 ...

Page 21

... Class I, II Table 1–21. Differential HSTL I/O Standards V (V) I/O CCIO Standard Min Typ Max HSTL-18 1.71 1.8 1.89 Class I HSTL-15 1.425 1.5 1.575 Class I, II HSTL-12 1.14 1.2 1.26 Class I, II December 2011 Altera Corporation V V IL(AC) IH(AC) V (V) IH(DC) (V) (V) Min Max Max Min REF REF REF — 0.1 0.175 0.175 ...

Page 22

... The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f For more information about power estimation tools, refer to the Estimator User Guide Handbook. December 2011 Altera Corporation (Note 1), (2) V (mV) V ...

Page 23

... REFCLK pin Rise/fall time (21) — Duty cycle — Peak-to-peak differential input — voltage Spread-spectrum modulating clock PCIe frequency December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 50 — ...

Page 24

... Delta time between — reconfig_clks (19) Transceiver block minimum power-down — (gxb_powerdown) pulse width Receiver December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ — ...

Page 25

... Gbps Equalization = 0 DC gain = 0.82 V ICM setting V ICM V = 1.1 V ICM setting (6) December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS 600 — ...

Page 26

... Gbps 3 dB Bandwidth in lock-to-data (LTD) Serial RapidIO mode 2.5 Gbps Serial RapidIO 3.125 Gbps GIGE SONET OC12 SONET OC48 December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ For more information about receiver DC coupling support, refer to the “ ...

Page 27

... Direct) Data rate (Single — width, PMA Direct) Data rate (Double width, PMA Direct) — (12) V 0.65 V setting OCM December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ — ...

Page 28

... Basic ×4 ×8 PMA and Inter-transceiver PCS bonded block transmitter mode Example: channel-to-channel PCIe ×8, skew Basic ×8 December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 85 ± ...

Page 29

... Supported Data — Range pll_powerdown minimum pulse — width (tpll_powerdown) CMU PLL lock time from — pll_powerdown de-assertion December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ — ...

Page 30

... Bandwidth (OIF) CEI PHY at 6.375 Gbps Transceiver-FPGA Fabric Interface Interface speed — (non-PMA Direct) Interface speed — (PMA Direct) December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military and Speed Grade –2× Commercial Speed Grade Min Typ Max Min Typ 2 ...

Page 31

... The rise and fall time transition is specified from 20% to 80%. (22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the December 2011 Altera Corporation –3 Commercial/ –2 Commercial ...

Page 32

... CDR) Absolute V for a MAX — REFCLK pin Operational V for MAX — a REFCLK pin Absolute V for a MIN — REFCLK pin December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ 50 — 706.25 50 — 706.25 50 — ...

Page 33

... Transceiver block minimum (gxb_powerdown) — power-down pulse width Receiver Supported I/O Standards Data rate (Single width, — non-PMA Direct) December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ — — 0.2 — — 45 — ...

Page 34

... DC gain = 0 dB pins for data rates > 10.3125 Gbps 0.82 V ICM setting V ICM V = 1.2 V ICM setting (5) December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ 1000 — 11300 1000 - 10312.5 1000 ...

Page 35

... DC Gain Setting = 1 Programmable DC DC Gain Setting gain = 2 DC Gain Setting = 3 DC Gain Setting = 4 EyeQ Max Data Rate — December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ 85 ± 20% 85 ± 20% 100 ± 20% 100 ± ...

Page 36

... V 0.65 V setting OCM 85 setting Differential on-chip 100 setting termination 120 setting resistors 150- setting December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ 2500 — ...

Page 37

... XAUI, PCIe, ×4, skew Basic ×4 ×8 PMA and Inter-transceiver PCS bonded block transmitter mode Example: channel-to-channel PCIe ×8, skew Basic ×8 December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ Compliant 50 — ...

Page 38

... ATX PLL (10G) Supported Data — Range Transceiver-FPGA Fabric Interface Interface speed — (non-PMA Direct) Interface speed — (PMA Direct) December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed Grade Grade Min Typ Max Min Typ — — 400 — ...

Page 39

... AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. December 2011 Altera Corporation –1 Industrial Speed – ...

Page 40

... Figure 1–2. Lock Time Parameters for Manual Mode r x_analogreset CDR status r x_locktodata Invalid Data r x_dataout Figure 1–3 shows the lock time parameters in automatic mode. Figure 1–3. Lock Time Parameters for Automatic Mode CDR status r x_freqlocked r x_dataout December 2011 Altera Corporation LTR t t LTR LTD_Manual t LTR_LTD_Manual LTR Invalid data t ...

Page 41

... Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part Pre-Emphasis 1st Post-Tap Setting N/A 0 N/A 1.5 December 2011 Altera Corporation Table 1–28 lists the typical differential V Setting, TX Term = 85  Setting (mV 170 ± 340 ± 510 ± 595 ± 20% ...

Page 42

... Switching Characteristics Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part Pre-Emphasis 1st Post-Tap Setting N N/A 2.7 6 N/A 3.1 7 N/A 3.7 8 N/A 4.2 9 N/A 4.9 10 N/A 5 N/A 6.8 13 N/A 7.5 14 N/A 8.1 15 N/A 8.8 16 N/A N/A 17 N/A N/A 18 N/A N/A 19 N/A N/A 20 N/A N/A 21 N/A N/A 22 N/A N/A 23 N/A N/A 24 N/A N/A 25 N/A N/A 26 N/A N/A 27 N/A N/A 28 N/A N/A 29 N/A N/A 30 N/A N/A 31 N/A N/A December 2011 Altera Corporation V Setting 0.7 0.3 0 1.2 0.5 0.3 1.3 0.8 0.5 1.8 1.1 0.7 2.1 1.3 0.9 2.4 1.6 1.2 2.8 1.9 1.4 3.2 2.2 1.7 3.5 2.6 1.9 3.8 2.8 2.1 4.2 3.1 2.3 4.5 3.4 2.6 4.9 3.7 2.9 5.3 4 3.1 5.7 4.4 3.4 6.1 4.7 3.6 6.6 5 5.4 4.3 8 6.1 4.8 9 6.8 5.4 10 7.6 6 11.4 8.4 6.8 12.6 9.4 7.4 N/A 10.3 8.1 N/A 11.3 8.8 N/A 12.5 9.6 N/A N/A 11.4 N/A N/A 12 ...

Page 43

... Fibre Channel Transmit Jitter Generation (4), Total jitter FC-1 Pattern = CRPAT Deterministic jitter FC-1 Pattern = CRPAT Total jitter FC-2 Pattern = CRPAT Deterministic jitter FC-2 Pattern = CRPAT December 2011 Altera Corporation –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade Min Typ Max ...

Page 44

... Compliance pattern (Gen1) Total jitter at 5 Gbps Compliance pattern (Gen2) (14) PCIe Receiver Jitter Tolerance (6) Total jitter at 2.5 Gbps Compliance pattern (Gen1) December 2011 Altera Corporation (Note 1), –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade Min Typ Max ...

Page 45

... Gbps Pattern = CJPAT GIGE Transmit Jitter Generation (8) Deterministic jitter Pattern = CRPAT (peak-to-peak) Total jitter Pattern = CRPAT (peak-to-peak) December 2011 Altera Corporation (Note –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade Min Typ Max ...

Page 46

... CEI Receiver Jitter Tolerance (10) Data Rate = 6.375 Gbps Deterministic jitter Pattern = PRBS31 BER = tolerance (peak-to-peak) -12 10 December 2011 Altera Corporation (Note –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade Min Typ Max Min > ...

Page 47

... Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz Alignment jitter (peak-to-peak) Data Rate = 2.97 Gbps (3G) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz December 2011 Altera Corporation (Note 1), (2) –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade ...

Page 48

... December 2011 Altera Corporation Switching Characteristics (Part –4 Commercial/ Industrial Speed Unit Grade Min Typ Max > > 0.3 UI > 0.3 UI > > 0.2 UI > 0.2 UI — — ...

Page 49

... Total jitter tolerance Pattern = CJTPAT E.6.LV, E.12.LV, E.24.LV, Deterministic jitter E.30.LV tolerance Pattern = CJTPAT E.6.LV, E.12.LV, E.24.LV, Combined deterministic E.30.LV and random jitter tolerance Pattern = CJTPAT December 2011 Altera Corporation (Note 1), (2) –3 Commercial/ –2 Commercial Industrial/Military Speed Grade and –2× Commercial Speed Grade Min Typ Max Min ...

Page 50

... Max — — 0.35 — — 0.35 — — 0.17 — — 0.17 > 0.37 > 0.37 > 0.55 > 0.55 > 8.5 > 8.5 > 0.1 > 0.1 > 8.5 > 8.5 > 0.1 > 0.1 December 2011 Altera Corporation Switching Characteristics (Part –4 Commercial/ Industrial Speed Unit Grade Min Typ Max — — 0.35 UI — — 0.17 UI > 0.37 UI > 0.55 UI > 8.5 UI > 0.1 UI > 8.5 UI > ...

Page 51

... The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification. (17) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0. (18) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1. December 2011 Altera Corporation (Note 1), (2) – ...

Page 52

... Switching Characteristics –3 Industrial Speed Grade Grade Unit Typ Max Min Typ Max — 0.30 — — 0.30 UI — 0.17 — — 0.17 UI > 0.62 — UI > 5 — UI > 0.05 — UI — 0.3 — — — UI — 0.30 — — 0.30 UI — 0.17 — — 0.17 UI December 2011 Altera Corporation ...

Page 53

... Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units characterized was 0.30 UI. (4) Contact Altera for board and link best practices at BER = 1E-15. December 2011 Altera Corporation –1 Industrial Speed –2 Industrial Speed ...

Page 54

... Performance –2/–2× Speed Grade –3 Speed Grade 800 700 550 500 Switching Characteristics Transceiver Transceiver Architecture in Transceiver Architecture in Transceiver Architecture in Transceiver Transceiver Architecture in Stratix Transceiver Unit –4 Speed Grade 500 MHz 450 MHz December 2011 Altera Corporation ...

Page 55

... Input clock cycle to cycle jitter (F t (4), (5) INCCJ Input clock cycle to cycle jitter (F Period Jitter for dedicated clock output (F t (6) OUTPJ_DC Period Jitter for dedicated clock output (F December 2011 Altera Corporation Parameter Min 600 600 600 40 — — — — — ...

Page 56

... The output jitter specification applies Table 1–50 on page 1–61. Switching Characteristics Typ Max Unit — 175 ps (p-p) — 17.5 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 250 ps (p-p) — 25 mUI (p-p) — ±10 % specification. VCO Table 1–48 on December 2011 Altera Corporation ...

Page 57

... Resources Used Memory Mode ALUTs Single port 0 64×10 Simple dual-port 0 32×20 MLAB (3) Simple dual-port 0 64×10 ROM 64×10 0 ROM 32×20 0 December 2011 Altera Corporation (Note Resources Used –2/–2× Number of Speed Multipliers Grade 1 520 1 540 1 600 1 480 4 490 ...

Page 58

... December 2011 Altera Corporation Unit MHz MHz MHz MHz MHz MHz MHz ps ps ...

Page 59

... For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed grade column. December 2011 Altera Corporation –3 –2 /–2× Commercia/ ...

Page 60

... V of the TDO JPCO CCIO Typ Max Unit A — 500 — 0.9 V  — < 5 — 1.030 — December 2011 Altera Corporation ...

Page 61

... HSCLK_in clock frequency) Clock boost factor Single Ended I/O (3) Standards (10) f (output HSCLK_OUT — clock frequency) December 2011 Altera Corporation Min 500 (Note 1), (2), (10) (Part 1 of 3)—Preliminary –2/–2× Speed Grade –3 Speed Grade Min Typ Max Min 5 — ...

Page 62

... December 2011 Altera Corporation Unit ...

Page 63

... For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed grade column. December 2011 Altera Corporation (Note 1), (2), (10) (Part 3 of 3)—Preliminary – ...

Page 64

... December 2011 Altera Corporation ...

Page 65

... Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than 1.25 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification 25 8.5 0.35 0 December 2011 Altera Corporation (Note Number of Data Number of Repetitions Transitions in One per 256 Data Transitions Repetition of the (4) Training Pattern ...

Page 66

... Switching Characteristics Sinusoidal Jitter (UI) 25.000 25.000 0.350 0.350 Frequency 20 MHz Number of DQS Delay Buffer Delay Mode (1) Chains Low 16 Low 12 Low 10 Low 8 High 12 High 10 High 8 December 2011 Altera Corporation ...

Page 67

... Note to Table 1–47: (1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –2/–2x speed grade is ± ± 39 ps. December 2011 Altera Corporation Available Phase Shift –3 –4 Speed Grade 470-590 60°, 120°, 180°, 240° ...

Page 68

... Switching Characteristics 1), (2), (3) –3 –4 Speed Grade Unit Max Min Max 55 - 110 -110 110 ps 82.5 -82.5 82.5 ps 82.5 -82.5 82.5 ps 165 -165 165 Min Typ Max Unit — — 20 MHz — 1000 — Cycles — 28 — Cycles — 2.5 — ns December 2011 Altera Corporation ...

Page 69

... The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. f The Excel-based I/O Timing spreadsheet is downloadable from the Stratix IV Devices December 2011 Altera Corporation Tristate RS_RT – ...

Page 70

... Slow Model C3 C4 I3/M3 I4 Unit 0.795 0.857 0.801 0.864 0.372 0.407 0.371 0.405 2.927 3.157 2.948 3.178 0.882 0.952 0.889 0.959 0.799 0.875 0.817 0.882 0.319 0.345 0.321 0.347 Typical Unit 0 (default 100 ps 150 ps December 2011 Altera Corporation ...

Page 71

... Left/right PLL input clock frequency. HSCLK High-speed I/O block: Maximum/minimum LVDS data transfer rate f HSDR 1/TUI), non-DPA. HSDR High-speed I/O block: Maximum/minimum LVDS data transfer rate f HSDRDPA (f HSDRDPA — December 2011 Altera Corporation Definitions — — ...

Page 72

... Chapter 1: DC and Switching Characteristics for Stratix IV Devices Definitions t JCP JCH JCL JPSU JPH t t JPZX JPCO — (1) Switchover INPFD N PFD Reconfigurable in User Mode External Feedback — Glossary t JPXZ CLKOUT Pins f OUT_EXT f GCLK Counters f VCO VCO OUT C0..C9 RCLK December 2011 Altera Corporation ...

Page 73

... Period jitter on the general purpose I/O driven by a PLL OUTPJ_IO t Period jitter on the dedicated clock output driven by a PLL OUTPJ_DC t Signal low-to-high transition time (20-80%) RISE U — December 2011 Altera Corporation Definitions Bit Time Sampling Window RSKM RSKM 0.5 x TCCS (SW) V REF — ...

Page 74

... Removed (Note 17) in Table 1-24. ■ February 2011 4.7 Added (Note 17) to Table 1–24. ■ Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter 1: DC and Switching Characteristics for Stratix IV Devices Definitions — Changes Figure 1–7. Table 1–22 and Table 1–41. Glossary December 2011 Altera Corporation ...

Page 75

... Updated Table 1–1, Table 1–2, Table 1–7, Table 1–10, Table 1–11, Table 1–12, ■ June 2009 3.1 Table 1–21, Table 1–22, Table 1–23, Table 1–25, Table 1–37, Table 1–38, Table 1–39, Table 1–40, and Table 1–44. Minor text edits. ■ December 2011 Altera Corporation Changes Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 1–67 ...

Page 76

... August 2008 1.1 repeated in the glossary. Minor text edits and an additional note to Table 1–26. ■ May 2008 1.0 Initial release. Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Chapter 1: DC and Switching Characteristics for Stratix IV Devices Changes December 2011 Altera Corporation Glossary ...

Page 77

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...

Page 78

... Chapter 2: Addendum to the Stratix IV Device Handbook Changes “Decision Feedback Equalization (DFE)” is published. “Adaptive Equalization (AEQ)” sections to the chapter. “Power-On Reset Circuitry” and “Power-On Reset Specifications” section now that AN 612: Decision Dynamic Reconfiguration in sections to chapter. – 4 commercial speed grade. February 2011 Altera Corporation ...

Page 79

... The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters italic type Initial Capital Letters “Subheading Title” December 2011 Altera Corporation (1) Contact Method Website Website Email Website Email Email ...

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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page of the Altera December 2011 Altera Corporation ...

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