EP4SGX230DF29C2XN

Manufacturer Part NumberEP4SGX230DF29C2XN
DescriptionIC STRATIX IV FPGA 230K 780FBGA
ManufacturerAltera Corporation
SeriesStratix® IV GX
EP4SGX230DF29C2XN datasheets

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Specifications of EP4SGX230DF29C2XN

Number Of Logic Elements/cells228000Number Of Labs/clbs9120
Total Ram Bits17544192Number Of I /o372
Number Of Gates-Voltage - Supply0.87 V ~ 0.93 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case780-BBGALead Free StatusLead free
Rohs StatusRoHS Compliant  
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PrevNext
2–2
Document Revision History
Table 2–5
lists the revision history for this chapter.
Table 2–1. Document Revision History
Date
Version
Removed the
■
Feedback Equalization in Stratix IV Devices
Moved the
■
Stratix IV Devices
February 2011
1.5
Moved the
■
the
Hot Socketing and Power-On Reset in Stratix IV Devices
Minor text edits.
■
Added corrections for the Adaptive Equalization (AEQ) section of the Stratix IV Dynamic
■
Reconfiguration chapter.
September 2010
1.4
Added new information for the Decision Feedback Equalization (DFE) feature.
■
Added corrections for the “Power-On Reset Circuitry” and “Power-On Reset
■
April 2010
1.3
Specifications” sections to of the Hot Socketing and Power-On Reset in Stratix IV Devices
chapter.
Moved the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correct
■
Power-Up Sequence for Production Devices”, and “Correct Power-Up Sequence for
Production Devices” sections to the Hot Socketing and Power-On Reset in Stratix IV
Devices chapter.
March 2010
1.2
Moved the “Power-On Reset Circuit” and “JTAG TMS and TDI Pin Pull-Up Resistor Value
■
Specification” sections to the Configuration, Design Security, Remote System Upgrades
with Stratix IV Devices chapter.
Moved the “Summary of OCT Assignments” section to the I/O Features in Stratix IV
■
Devices chapter.
Added the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correction to
■
POR Signal Pulse Width Delay Times”, “Correct Power-Up Sequence for Production
Devices”, “Power-On Reset Circuit”, “Summary of OCT Assignments”, and “JTAG TMS
February 2010
1.1
and TDI Pin Pull-Up Resistor Value Specification” sections.
Minor text edits.
■
Stratix IV GX enhanced transceiver data rate specifications in
■
November 2009
1.0
Initial release.
■
Stratix IV Device Handbook Volume 4
Chapter 2: Addendum to the Stratix IV Device Handbook
Changes
“Decision Feedback Equalization (DFE)”
is published.
“Adaptive Equalization (AEQ)”
sections to the
chapter.
“Power-On Reset Circuitry”
and
“Power-On Reset Specifications”
section now that
AN 612: Decision
Dynamic Reconfiguration in
sections to
chapter.
– 4 commercial speed grade.
February 2011 Altera Corporation

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