5M160ZM100I5N Altera Corporation, 5M160ZM100I5N Datasheet - Page 30

• Manufacturer Part Number: 5M160ZM100I5N
• Description: IC MAX V CPLD 160 LE 100-MBGA
• Manufacturer: Altera Corporation
• Series: MAX® Vr

Specifications of 5M160ZM100I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 160
• Number Of Macrocells: 128
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 100-TFBGA
• Lead Free Status: Vendor undefined
• Rohs Status: RoHS Compliant

3–30
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)
Document Revision History
Table 3–42. Document Revision History
MAX V Device Handbook
t
Notes to
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO degrades the maximum TCK frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and
May 2011
January 2011
December 2010
JSXZ
1.5-V LVCMOS operation, the t
Symbol
Date
Table
3–41:
Table 3–42
Update register valid output to high impedance
Version
1.2
1.1
1.0
JPSU
minimum is 6 ns and t
lists the revision history for this chapter.
Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.
Updated
Initial release.
Parameter
Table
JPCO
, t
3–2,
JPZX
, and t
Table
JPXZ
3–15,
Chapter 3: DC and Switching Characteristics for MAX V Devices
are maximum values at 35 ns.
Table
Changes
3–16, and
Min
—
Table
3–33.
May 2011 Altera Corporation
Max
Document Revision History
25
Unit
ns