5M1270ZT144C4N Altera Corporation, 5M1270ZT144C4N Datasheet - Page 29

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5M1270ZT144C4N

Manufacturer Part Number
5M1270ZT144C4N
Description
IC MAX V CPLD 1270 LE 144-TQFP
Manufacturer
Altera Corporation
Series
MAX® Vr
Datasheet

Specifications of 5M1270ZT144C4N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of Gates
-
Number Of I /o
114
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status
Vendor undefined
Rohs Status
RoHS Compliant

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Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Figure 3–6. JTAG Timing Waveform for MAX V Devices
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
May 2011 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
(1)
Symbol
JTAG Timing Specifications
Captured
Figure 3–6
family.
Table 3–41
TCK clock period for V
TCK clock period for V
TCK clock period for V
TCK clock period for V
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
shows the timing waveform for the JTAG signals for the MAX V device
lists the JTAG timing parameters and values for the MAX V device family.
t
JCH
t
JPZX
t
JSZX
t
JCP
t
JSSU
CCIO1
CCIO1
CCIO1
CCIO1
(2)
t
Parameter
JCL
(2)
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
t
JSH
t
t
JPCO
JSCO
t
JPSU
(2)
(2)
t
JSXZ
t
JPH
t
55.5
62.5
JPXZ
Min
100
143
20
20
10
10
8
8
Max
15
15
15
25
25
MAX V Device Handbook
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3–29

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